[gcc r15-5224] [PATCH] RISC-V: Bugfix for unrecognizable insn for XTheadVector

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:8564d0948c72df0a66d7eb47e15c6ab43e9b25ce

commit r15-5224-g8564d0948c72df0a66d7eb47e15c6ab43e9b25ce
Author: Jin Ma <ji...@linux.alibaba.com>
Date:   Wed Nov 13 15:19:29 2024 -0700

    [PATCH] RISC-V: Bugfix for unrecognizable insn for XTheadVector
    
    error: unrecognizable insn:
    
    (insn 35 34 36 2 (set (subreg:RVVM1SF (reg/v:RVVM1x4SF 142 [ _r ]) 0)
            (unspec:RVVM1SF [
                    (const_vector:RVVM1SF repeat [
                            (const_double:SF 0.0 [0x0.0p+0])
                        ])
                    (reg:DI 0 zero)
                    (const_int 1 [0x1])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_TH_VWLDST)) -1
         (nil))
    during RTL pass: mode_sw
    
            PR target/116591
    
    gcc/ChangeLog:
    
            * config/riscv/vector.md: Add restriction to call pred_th_whole_mov.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/xtheadvector/pr116591.c: New test.

Diff:
---
 gcc/config/riscv/vector.md                                 |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c | 14 ++++++++++++++
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 8bbae41c9f32..c29e69d5c36d 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1175,7 +1175,7 @@
        - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
         before spilling. The clobber scratch is used by spilling fractional
         registers in IRA/LRA so it's too early.  */
-  if (TARGET_XTHEADVECTOR)
+  if (TARGET_XTHEADVECTOR && reg_or_mem_operand (operands[1], <MODE>mode))
     {
       emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1],
                                        RVV_VLMAX, 
GEN_INT(riscv_vector::VLMAX)));
@@ -1238,7 +1238,7 @@
        (match_operand:VB 1 "general_operand"))]
   "TARGET_VECTOR"
 {
-  if (TARGET_XTHEADVECTOR)
+  if (TARGET_XTHEADVECTOR && reg_or_mem_operand (operands[1], <MODE>mode))
     {
       emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1],
                                        RVV_VLMAX, 
GEN_INT(riscv_vector::VLMAX)));
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c
new file mode 100644
index 000000000000..dfaf82ce1ca8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c
@@ -0,0 +1,14 @@
+/* { dg-do assemble } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32d -O2 -save-temps" { 
target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2 -save-temps" { 
target { rv64 } } } */
+
+#include <riscv_vector.h>
+
+void
+foo (float *a, int b)
+{
+  vfloat32m1x4_t c;
+  __riscv_vsseg4e32_v_f32m1x4(a, c, b);
+}
+
+/* { dg-final { scan-assembler-times {th\.vmv\.v\.i\tv[0-9]+,0} 4 } } */