https://gcc.gnu.org/g:292a657f3027ab3036ad9e7efcafde2b679bec7f
commit 292a657f3027ab3036ad9e7efcafde2b679bec7f
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Nov 6 16:15:36 2024 -0500
Add debugging for PR 71977-1.c regression.
2024-11-06 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (sf_logical_op_p): New function.
* config/rs6000/rs6000.h (sf_logical_op_p): Add declaration.
* config/rs6000/vsx.md (define_peephole2 for SF + logical): Move
test to
sf_logical_op_p.
Diff:
---
gcc/config/rs6000/rs6000.cc | 62 +++++++++++++++++++++++++++++++++++++++++++++
gcc/config/rs6000/rs6000.h | 2 ++
gcc/config/rs6000/vsx.md | 19 +-------------
3 files changed, 65 insertions(+), 18 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index aa67e7256bb9..e1ec9591a0eb 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -29564,6 +29564,68 @@ rs6000_opaque_type_invalid_use_p (gimple *stmt)
return false;
}
+bool
+sf_logical_op_p (rtx operands[])
+{
+ if (!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE)
+ {
+ fprintf (stderr, "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE\n");
+ return false;
+ }
+
+ /* The REG_P (xxx) tests prevents SUBREG's, which allows us to use REGNO
+ to compare registers, when the mode is different. */
+ if (!REG_P (operands[SFBOOL_MFVSR_D]) && REG_P (operands[SFBOOL_BOOL_D]))
+ {
+ fprintf (stderr, "REG_P (operands[SFBOOL_MFVSR_D]) && REG_P
(operands[SFBOOL_BOOL_D]))\n");
+ return false;
+ }
+
+ if (!REG_P (operands[SFBOOL_BOOL_A1]) && REG_P (operands[SFBOOL_SHL_D]))
+ {
+ fprintf (stderr, "!REG_P (operands[SFBOOL_BOOL_A1]) && REG_P
(operands[SFBOOL_SHL_D])\n");
+ return false;
+ }
+
+ if (!REG_P (operands[SFBOOL_SHL_A]) && REG_P (operands[SFBOOL_MTVSR_D]))
+ {
+ fprintf (stderr, "!REG_P (operands[SFBOOL_SHL_A]) && REG_P
(operands[SFBOOL_MTVSR_D])\n");
+ return false;
+ }
+
+ if (!REG_P (operands[SFBOOL_BOOL_A2])
+ && !CONST_INT_P (operands[SFBOOL_BOOL_A2]))
+ {
+ fprintf (stderr, "!REG_P (operands[SFBOOL_BOOL_A2]) && !CONST_INT_P
(operands[SFBOOL_BOOL_A2])\n");
+ return false;
+ }
+
+ if (!REGNO (operands[SFBOOL_BOOL_D]) == REGNO (operands[SFBOOL_MFVSR_D])
+ && !peep2_reg_dead_p (2, operands[SFBOOL_MFVSR_D]))
+ {
+ fprintf (stderr, "!REGNO (operands[SFBOOL_BOOL_D]) == REGNO
(operands[SFBOOL_MFVSR_D]) && !peep2_reg_dead_p (2,
operands[SFBOOL_MFVSR_D])\n");
+ return false;
+ }
+
+ if (((REGNO (operands[SFBOOL_MFVSR_D]) == REGNO (operands[SFBOOL_BOOL_A1])
+ || (REG_P (operands[SFBOOL_BOOL_A2])
+ && REGNO (operands[SFBOOL_MFVSR_D]) == REGNO
(operands[SFBOOL_BOOL_A2])))
+ && REGNO (operands[SFBOOL_BOOL_D]) == REGNO (operands[SFBOOL_SHL_A])
+ && (REGNO (operands[SFBOOL_SHL_D]) == REGNO (operands[SFBOOL_BOOL_D])
+ || peep2_reg_dead_p (3, operands[SFBOOL_BOOL_D]))
+ && peep2_reg_dead_p (4, operands[SFBOOL_SHL_D])))
+ {
+ fprintf (stderr, "last test passed\n");
+ return true;
+ }
+ else
+ {
+ fprintf (stderr, "last test failed\n");
+ return false;
+ }
+}
+
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8cfd9faf77dc..499e80fda08d 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2525,3 +2525,5 @@ enum {
#undef ARCH_EXPAND
#endif /* GCC_HWINT_H. */
+
+extern bool sf_logical_op_p (rtx operands[]);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b2fc39acf4e8..bcf8e2a60462 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -6338,24 +6338,7 @@
(set (match_operand:SF SFBOOL_MTVSR_D "vsx_register_operand")
(unspec:SF [(match_dup SFBOOL_SHL_D)] UNSPEC_P8V_MTVSRD))]
- "TARGET_POWERPC64 && TARGET_DIRECT_MOVE
- /* The REG_P (xxx) tests prevents SUBREG's, which allows us to use REGNO
- to compare registers, when the mode is different. */
- && REG_P (operands[SFBOOL_MFVSR_D]) && REG_P (operands[SFBOOL_BOOL_D])
- && REG_P (operands[SFBOOL_BOOL_A1]) && REG_P (operands[SFBOOL_SHL_D])
- && REG_P (operands[SFBOOL_SHL_A]) && REG_P (operands[SFBOOL_MTVSR_D])
- && (REG_P (operands[SFBOOL_BOOL_A2])
- || CONST_INT_P (operands[SFBOOL_BOOL_A2]))
- && (REGNO (operands[SFBOOL_BOOL_D]) == REGNO (operands[SFBOOL_MFVSR_D])
- || peep2_reg_dead_p (2, operands[SFBOOL_MFVSR_D]))
- && (REGNO (operands[SFBOOL_MFVSR_D]) == REGNO (operands[SFBOOL_BOOL_A1])
- || (REG_P (operands[SFBOOL_BOOL_A2])
- && REGNO (operands[SFBOOL_MFVSR_D])
- == REGNO (operands[SFBOOL_BOOL_A2])))
- && REGNO (operands[SFBOOL_BOOL_D]) == REGNO (operands[SFBOOL_SHL_A])
- && (REGNO (operands[SFBOOL_SHL_D]) == REGNO (operands[SFBOOL_BOOL_D])
- || peep2_reg_dead_p (3, operands[SFBOOL_BOOL_D]))
- && peep2_reg_dead_p (4, operands[SFBOOL_SHL_D])"
+ "sf_logical_op_p (operands)"
[(set (match_dup SFBOOL_TMP_GPR)
(ashift:DI (match_dup SFBOOL_BOOL_A_DI)
(const_int 32)))
