https://gcc.gnu.org/g:95e4e093c98f18dd4cdbb26a0a6d2f4929e5b2a9
commit 95e4e093c98f18dd4cdbb26a0a6d2f4929e5b2a9
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Oct 22 19:37:19 2024 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.sha | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/gcc/ChangeLog.sha b/gcc/ChangeLog.sha
index d33f88b871de..402ab7534d33 100644
--- a/gcc/ChangeLog.sha
+++ b/gcc/ChangeLog.sha
@@ -1,5 +1,40 @@
+==================== Branch work182-sha, patch #400 ====================
+
+Initial support for adding xxeval fusion support.
+
+2024-10-16 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ PR target/117251
+ * config/rs6000/fusion.md: Regenerate.
+ * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support to
+ generate vector/vector logical fusion if XXEVAL supports the fusion.
+ * config/rs6000/predicates.md (vector_fusion_operand): New predicate.
+ * config/rs6000/rs6000.cc (rs6000_opt_vars): Add -mxxeval.
+ * config/rs6000/rs6000.md (isa attribute): Add xxeval.
+ (enabled attribute): Add support for -mxxeval.
+ * config/rs6000/rs6000.opt (-mxxeval): New switch.
+
+gcc/testsuite/
+
+ PR target/117251
+ * gcc.target/powerpc/p10-vector-fused-1.c: New test.
+ * gcc.target/powerpc/p10-vector-fused-2.c: Likewise.
+ * gcc.target/powerpc/xxeval-1.c: Likewise.
+ * gcc.target/powerpc/xxeval-2.c: Likewise.
+
==================== Branch work182-sha, baseline ====================
+Add ChangeLog.sha and update REVISION.
+
+2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * ChangeLog.sha: New file for branch.
+ * REVISION: Update.
+
2024-10-22 Michael Meissner <meiss...@linux.ibm.com>
Clone branch
