https://gcc.gnu.org/g:b5d3ebf29245858d673712a28d970adf5d8766cb
commit b5d3ebf29245858d673712a28d970adf5d8766cb
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Nov 6 13:42:04 2024 -0500
Add rs6000 architecture masks.
This patch begins the journey to move architecture bits that are not user
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to
use
-mcpu=power10 and not just -mpower10.
This patch also changes the target_clones support to use an architecture
mask
instead of isa bits.
This patch also switches the handling of .machine to use architecture masks
if
they exist (power4 through power11). All of the other PowerPCs will
continue to
use the existing code for setting the .machine option.
I have built both big endian and little endian bootstrap compilers and there
were no regressions.
In addition, I constructed a test case that used every archiecture define
(like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I
ran
this test for all supported combinations of -mcpu, big/little endian, and
32/64
bit support. Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.
Can I install this patch on the GCC 15 trunk?
2024-11-06 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (struct clone_map): Switch to using
architecture masks instead of ISA masks.
(rs6000_clone_map): Likewise.
(rs6000_print_isa_options): Add an architecture flags argument,
change
all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Switch to using architecture masks
instead
of ISA masks.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_clone_priority): Switch to using architecture masks instead
of
ISA masks.
(rs6000_can_inline_p): Don't allow inling if the callee requires a
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 27 +++++++++++++++------------
gcc/config/rs6000/rs6000-cpus.def | 8 +-------
gcc/config/rs6000/rs6000-protos.h | 5 +++--
gcc/config/rs6000/rs6000.cc | 19 +++++++++++--------
gcc/config/rs6000/rs6000.h | 20 ++++++++++++++++++++
gcc/config/rs6000/rs6000.opt | 11 ++---------
6 files changed, 52 insertions(+), 38 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 04882c396bfe..c8f33289fa38 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char
*name)
#pragma GCC target, we need to adjust the macros dynamically. */
void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+ HOST_WIDE_INT arch_flags)
{
if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
summary of the flags associated with particular cpu
definitions. */
- /* rs6000_isa_flags based options. */
+ /* rs6000_isa_flags and rs6000_arch_flags based options. */
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,23 +420,25 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
if ((flags & OPTION_MASK_POWERPC64) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
- if ((flags & OPTION_MASK_MFCRF) != 0)
+ if ((flags & OPTION_MASK_POWERPC64) != 0)
+ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
+ if ((arch_flags & ARCH_MASK_POWER4) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
- if ((flags & OPTION_MASK_POPCNTB) != 0)
+ if ((arch_flags & ARCH_MASK_POWER5) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
- if ((flags & OPTION_MASK_FPRND) != 0)
+ if ((arch_flags & ARCH_MASK_POWER5X) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
- if ((flags & OPTION_MASK_CMPB) != 0)
+ if ((arch_flags & ARCH_MASK_POWER6) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
- if ((flags & OPTION_MASK_POPCNTD) != 0)
+ if ((arch_flags & ARCH_MASK_POWER7) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
- if ((flags & OPTION_MASK_POWER8) != 0)
+ if ((arch_flags & ARCH_MASK_POWER8) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
- if ((flags & OPTION_MASK_MODULO) != 0)
+ if ((arch_flags & ARCH_MASK_POWER9) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
- if ((flags & OPTION_MASK_POWER10) != 0)
+ if ((arch_flags & ARCH_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
- if ((flags & OPTION_MASK_POWER11) != 0)
+ if ((arch_flags & ARCH_MASK_POWER11) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
@@ -605,7 +608,7 @@ void
rs6000_cpu_cpp_builtins (cpp_reader *pfile)
{
/* Define all of the common macros. */
- rs6000_target_modify_macros (true, rs6000_isa_flags);
+ rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_arch_flags);
if (TARGET_FRE)
builtin_define ("__RECIP__");
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..a3568898b0b6 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,7 +47,6 @@
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
- | OPTION_MASK_POWER8 \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
@@ -83,11 +82,9 @@
| OPTION_MASK_PREFIXED)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
- | OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
-#define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
- | OPTION_MASK_POWER11)
+#define POWER11_MASKS_SERVER ISA_3_1_MASKS_SERVER
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
@@ -125,8 +122,6 @@
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
- | OPTION_MASK_POWER10 \
- | OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
@@ -135,7 +130,6 @@
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
- | OPTION_MASK_POWER8 \
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index b40557a85577..da658cd5ab2e 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -323,8 +323,9 @@ extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
extern bool rs6000_pragma_target_parse (tree, tree);
#endif
extern void rs6000_activate_target_options (tree new_tree);
-extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT);
-extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
+extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT);
+extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT,
+ HOST_WIDE_INT);
#ifdef NO_DOLLAR_IN_LABEL
const char * rs6000_xcoff_strip_dollar (const char *);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3f0ab23eeb4f..8388542b7210 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -278,7 +278,7 @@ bool cpu_builtin_p = false;
/* Pointer to function (in rs6000-c.cc) that can define or undefine target
macros that have changed. Languages that don't support the preprocessor
don't link in rs6000-c.cc, so we can't call it directly. */
-void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
+void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
/* Simplfy register classes into simpler classifications. We assume
GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
@@ -3904,8 +3904,7 @@ rs6000_option_override_internal (bool global_init_p)
/* If little-endian, default to -mstrict-align on older processors. */
if (!BYTES_BIG_ENDIAN
- && !(processor_target_table[tune_index].target_enable
- & OPTION_MASK_POWER8))
+ && (get_arch_flags (tune_index) & ARCH_MASK_POWER8) == 0)
rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
/* Add some warnings for VSX. */
@@ -24580,8 +24579,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false,
true },
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
- { "power10", OPTION_MASK_POWER10, false, true },
- { "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
@@ -25013,6 +25010,7 @@ rs6000_pragma_target_parse (tree args, tree pop_target)
tree cur_tree;
struct cl_target_option *prev_opt, *cur_opt;
HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
+ HOST_WIDE_INT prev_arch, cur_arch, diff_arch;
if (TARGET_DEBUG_TARGET)
{
@@ -25065,21 +25063,26 @@ rs6000_pragma_target_parse (tree args, tree
pop_target)
{
prev_opt = TREE_TARGET_OPTION (prev_tree);
prev_flags = prev_opt->x_rs6000_isa_flags;
+ prev_arch = prev_opt->x_rs6000_arch_flags;
cur_opt = TREE_TARGET_OPTION (cur_tree);
cur_flags = cur_opt->x_rs6000_isa_flags;
+ cur_arch = cur_opt->x_rs6000_arch_flags;
diff_flags = (prev_flags ^ cur_flags);
+ diff_arch = (prev_arch ^ cur_arch);
- if (diff_flags != 0)
+ if (diff_flags != 0 || diff_arch != 0)
{
/* Delete old macros. */
rs6000_target_modify_macros_ptr (false,
- prev_flags & diff_flags);
+ prev_flags & diff_flags,
+ prev_arch & diff_arch);
/* Define new macros. */
rs6000_target_modify_macros_ptr (true,
- cur_flags & diff_flags);
+ cur_flags & diff_flags,
+ cur_arch & diff_arch);
}
}
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2b81fdadc653..7ad8baca177a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -520,6 +520,26 @@ extern int rs6000_vector_align[];
#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
#endif
+/* In the past we represented the various power cpus (power4, power5, power6,
+ etc.) via ISA bits that highlighted a new instruction or we used an extra
+ option to represent the hardware (i.e. -mpower8-internal or -mpower10). Now
+ we use architecture flags for this. */
+#define TARGET_POWER4 ((rs6000_arch_flags & ARCH_MASK_POWER4) != 0)
+#define TARGET_POWER5 ((rs6000_arch_flags & ARCH_MASK_POWER5) != 0)
+#define TARGET_POWER5X ((rs6000_arch_flags & ARCH_MASK_POWER5X) != 0)
+#define TARGET_POWER6 ((rs6000_arch_flags & ARCH_MASK_POWER6) != 0)
+#define TARGET_POWER7 ((rs6000_arch_flags & ARCH_MASK_POWER7) != 0)
+#define TARGET_POWER8 ((rs6000_arch_flags & ARCH_MASK_POWER8) != 0)
+#define TARGET_POWER9 ((rs6000_arch_flags & ARCH_MASK_POWER9) != 0)
+#define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
+#define TARGET_POWER11 ((rs6000_arch_flags & ARCH_MASK_POWER11) != 0)
+
+/* In the past we represented power8, power10 as an ISA bit and used internal
+ switches the user was not supposed to use for -mpower8-internal and
+ -mpower10. Now we use architecture flags for this. */
+#define TARGET_POWER8 ((rs6000_arch_flags & ARCH_MASK_POWER8) != 0)
+#define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
+
/* For power systems, we want to enable Altivec and VSX builtins even if the
user did not use -maltivec or -mvsx to allow the builtins to be used inside
of #pragma GCC target or the target attribute to change the code level for a
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 73dfb63a81ce..0d71dbaf2fc1 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -478,9 +478,8 @@ Save the TOC in the prologue for indirect calls rather than
inline.
mvsx-timode
Target RejectNegative Undocumented Ignore
-;; This option exists only to create its MASK. It is not intended for users.
mpower8-internal
-Target Undocumented Mask(POWER8) Var(rs6000_isa_flags) Warn(Do not use
%<-mpower8-internal%>; use %<-mcpu=power8%> instead)
+Target Undocumented WarnRemoved
mpower8-fusion
Target Mask(P8_FUSION) Var(rs6000_isa_flags)
@@ -591,13 +590,7 @@ mspeculate-indirect-jumps
Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
mpower10
-Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
-
-;; Users should not use -mpower11, but we need to use a bit to identify when
-;; the user changes the default cpu via #pragma GCC target("cpu=power11")
-;; and then resets it later.
-mpower11
-Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) WarnRemoved
+Target Undocumented WarnRemoved
mprefixed
Target Mask(PREFIXED) Var(rs6000_isa_flags)
