https://gcc.gnu.org/g:0f27c445e6267e0a544ae030a2fb9e7058fc8ec0
commit 0f27c445e6267e0a544ae030a2fb9e7058fc8ec0
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Oct 24 12:11:15 2024 -0400
Revert changes
Diff:
---
gcc/config/rs6000/altivec.md | 35 +-
gcc/config/rs6000/predicates.md | 26 -
gcc/config/rs6000/rs6000.h | 3 -
gcc/config/rs6000/rs6000.md | 6 +-
.../gcc.target/powerpc/p10-vector-fused-1.c | 409 ---------
.../gcc.target/powerpc/p10-vector-fused-2.c | 936 ---------------------
.../gcc.target/powerpc/vector-rotate-left.c | 34 -
7 files changed, 5 insertions(+), 1444 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index d4ee50322ca1..00dad4b91f1c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1983,39 +1983,12 @@
}
[(set_attr "type" "vecperm")])
-;; -mcpu=future adds a vector rotate left word variant. There is no vector
-;; byte/half-word/double-word/quad-word rotate left. This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-;; However for testing, allow other xvrl variants. In particular, XVRLD for
-;; the sha3 tests for multibuf/singlebuf.
(define_insn "altivec_vrl<VI_char>"
- [(set (match_operand:VI2 0 "register_operand" "=v,wa")
- (rotate:VI2 (match_operand:VI2 1 "register_operand" "v,wa")
- (match_operand:VI2 2 "register_operand" "v,wa")))]
+ [(set (match_operand:VI2 0 "register_operand" "=v")
+ (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
+ (match_operand:VI2 2 "register_operand" "v")))]
"<VI_unit>"
- "@
- vrl<VI_char> %0,%1,%2
- xvrl<VI_char> %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")
- (set_attr "isa" "*,xvrlw")])
-
-(define_insn "*altivec_vrl<VI_char>_immediate"
- [(set (match_operand:VI2 0 "register_operand" "=wa,wa,wa,wa")
- (rotate:VI2 (match_operand:VI2 1 "register_operand" "wa,wa,wa,wa")
- (match_operand:VI2 2 "vector_shift_immediate"
"j,wM,wE,wS")))]
- "TARGET_XVRLW && <VI_unit>"
-{
- rtx op2 = operands[2];
- int value = 256;
- int num_insns = -1;
-
- if (!xxspltib_constant_p (op2, <MODE>mode, &num_insns, &value))
- gcc_unreachable ();
-
- operands[3] = GEN_INT (value & 0xff);
- return "xvrl<VI_char>i %x0,%x1,%3";
-}
+ "vrl<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vrlq"
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index fccfbd7e4904..1d95e34557e5 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -728,32 +728,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR whose elements are all the
-;; same and the elements can be an immediate shift or rotate factor
-(define_predicate "vector_shift_immediate"
- (match_code "const_vector,vec_duplicate,const_int")
-{
- int value = 256;
- int num_insns = -1;
-
- if (zero_constant (op, mode) || all_ones_constant (op, mode))
- return true;
-
- if (!xxspltib_constant_p (op, mode, &num_insns, &value))
- return false;
-
- switch (mode)
- {
- case V16QImode: return IN_RANGE (value, 0, 7);
- case V8HImode: return IN_RANGE (value, 0, 15);
- case V4SImode: return IN_RANGE (value, 0, 31);
- case V2DImode: return IN_RANGE (value, 0, 63);
- default: break;
- }
-
- return false;
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 1a168c2c9596..8cfd9faf77dc 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -581,9 +581,6 @@ extern int rs6000_vector_align[];
below. */
#define RS6000_FN_TARGET_INFO_HTM 1
-/* Whether we have XVRLW support. */
-#define TARGET_XVRLW TARGET_FUTURE
-
/* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 420f20d4524b..68fbfec95546 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -369,7 +369,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,xxeval,xvrlw"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,xxeval"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -426,10 +426,6 @@
(match_test "TARGET_PREFIXED && TARGET_XXEVAL"))
(const_int 1)
- (and (eq_attr "isa" "xvrlw")
- (match_test "TARGET_XVRLW"))
- (const_int 1)
-
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-1.c
b/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-1.c
deleted file mode 100644
index 28e0874b3454..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-1.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/* { dg-do run } */
-/* { dg-require-effective-target power10_hw } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Generate and check most of the vector logical instruction combinations that
- may or may not generate xxeval to do a fused operation on power10. */
-
-#include <stddef.h>
-#include <stdlib.h>
-#include <altivec.h>
-
-#ifdef DEBUG
-#include <stdio.h>
-
-static int errors = 0;
-static int tests = 0;
-#endif
-
-typedef vector unsigned int vector_t;
-typedef unsigned int scalar_t;
-
-/* Vector logical functions. */
-static inline vector_t
-vector_and (vector_t x, vector_t y)
-{
- return x & y;
-}
-
-static inline vector_t
-vector_or (vector_t x, vector_t y)
-{
- return x | y;
-}
-
-static inline vector_t
-vector_xor (vector_t x, vector_t y)
-{
- return x ^ y;
-}
-
-static inline vector_t
-vector_andc (vector_t x, vector_t y)
-{
- return x & ~y;
-}
-
-static inline vector_t
-vector_orc (vector_t x, vector_t y)
-{
- return x | ~y;
-}
-
-static inline vector_t
-vector_nand (vector_t x, vector_t y)
-{
- return ~(x & y);
-}
-
-static inline vector_t
-vector_nor (vector_t x, vector_t y)
-{
- return ~(x | y);
-}
-
-static inline vector_t
-vector_eqv (vector_t x, vector_t y)
-{
- return ~(x ^ y);
-}
-
-/* Scalar logical functions. */
-static inline scalar_t
-scalar_and (scalar_t x, scalar_t y)
-{
- return x & y;
-}
-
-static inline scalar_t
-scalar_or (scalar_t x, scalar_t y)
-{
- return x | y;
-}
-
-static inline scalar_t
-scalar_xor (scalar_t x, scalar_t y)
-{
- return x ^ y;
-}
-
-static inline scalar_t
-scalar_andc (scalar_t x, scalar_t y)
-{
- return x & ~y;
-}
-
-static inline scalar_t
-scalar_orc (scalar_t x, scalar_t y)
-{
- return x | ~y;
-}
-
-static inline scalar_t
-scalar_nand (scalar_t x, scalar_t y)
-{
- return ~(x & y);
-}
-
-static inline scalar_t
-scalar_nor (scalar_t x, scalar_t y)
-{
- return ~(x | y);
-}
-
-static inline scalar_t
-scalar_eqv (scalar_t x, scalar_t y)
-{
- return ~(x ^ y);
-}
-
-
-/*
- * Generate one function for each combination that we are checking. Do 4
- * operations:
- *
- * Use FPR regs that should generate either XXEVAL or XXL* insns;
- * Use Altivec registers than may generated fused V* insns;
- * Use VSX registers, insure fusing it not done via asm; (and)
- * Use GPR registers on scalar operations.
- */
-
-#ifdef DEBUG
-#define TRACE(INNER, OUTER) \
- do { \
- tests++; \
- printf ("%s_%s\n", INNER, OUTER); \
- fflush (stdout); \
- } while (0) \
-
-#define FAILED(INNER, OUTER) \
- do { \
- errors++; \
- printf ("%s_%s failed\n", INNER, OUTER); \
- fflush (stdout); \
- } while (0) \
-
-#else
-#define TRACE(INNER, OUTER)
-#define FAILED(INNER, OUTER) abort ()
-#endif
-
-#define FUSED_FUNC(INNER, OUTER) \
-static void \
-INNER ## _ ## OUTER (vector_t a, vector_t b, vector_t c) \
-{ \
- vector_t f_a, f_b, f_c, f_r, f_t; \
- vector_t v_a, v_b, v_c, v_r, v_t; \
- vector_t w_a, w_b, w_c, w_r, w_t; \
- scalar_t s_a, s_b, s_c, s_r, s_t; \
- \
- TRACE (#INNER, #OUTER); \
- \
- f_a = a; \
- f_b = b; \
- f_c = c; \
- \
- __asm__ (" # fpr regs: %x0,%x1,%x2 " #INNER "_" #OUTER \
- : "+d" (f_a), \
- "+d" (f_b), \
- "+d" (f_c)); \
- \
- f_t = vector_ ## INNER (f_b, f_c); \
- f_r = vector_ ## OUTER (f_a, f_t); \
- \
- __asm__ (" # fpr regs result: %x0 " #INNER "_" #OUTER
\
- : "+d" (f_r)); \
- \
- v_a = a; \
- v_b = b; \
- v_c = c; \
- \
- __asm__ (" # altivec regs: %x0,%x1,%x2 " #INNER "_" #OUTER \
- : "+v" (v_a), \
- "+v" (v_b), \
- "+v" (v_c)); \
- \
- v_t = vector_ ## INNER (v_b, v_c); \
- v_r = vector_ ## OUTER (v_a, v_t); \
- \
- __asm__ (" # altivec regs result: %x0 " #INNER "_" #OUTER \
- : "+v" (v_r)); \
- \
- w_a = a; \
- w_b = b; \
- w_c = c; \
- \
- __asm__ (" # vsx regs: %x0,%x1,%x2 " #INNER "_" #OUTER \
- : "+wa" (w_a), \
- "+wa" (w_b), \
- "+wa" (w_c)); \
- \
- w_t = vector_ ## INNER (w_b, w_c); \
- __asm__ ("nop # break vsx fusion reg %x0" : "+wa" (w_t)); \
- w_r = vector_ ## OUTER (w_a, w_t); \
- \
- __asm__ (" # vsx regs result: %x0 " #INNER "_" #OUTER
\
- : "+wa" (w_r)); \
- \
- s_a = a[0]; \
- s_b = b[0]; \
- s_c = c[0]; \
- \
- __asm__ (" # gpr regs: %0,%1,%2 " #INNER "_" #OUTER \
- : "+r" (s_a), \
- "+r" (s_b), \
- "+r" (s_c)); \
- \
- s_t = scalar_ ## INNER (s_b, s_c); \
- s_r = scalar_ ## OUTER (s_a, s_t); \
- \
- __asm__ (" # gpr regs result: %0 " #INNER "_" #OUTER \
- : "+r" (s_r)); \
- \
- if (!vec_all_eq (w_r, f_r) \
- || !vec_all_eq (w_r, v_r)
\
- || s_r != w_r[0])
\
- FAILED (#INNER, #OUTER); \
- \
- return; \
-}
-
-FUSED_FUNC (and, and)
-FUSED_FUNC (andc, and)
-FUSED_FUNC (eqv, and)
-FUSED_FUNC (nand, and)
-FUSED_FUNC (nor, and)
-FUSED_FUNC (or, and)
-FUSED_FUNC (orc, and)
-FUSED_FUNC (xor, and)
-
-FUSED_FUNC (and, andc)
-FUSED_FUNC (andc, andc)
-FUSED_FUNC (eqv, andc)
-FUSED_FUNC (nand, andc)
-FUSED_FUNC (nor, andc)
-FUSED_FUNC (or, andc)
-FUSED_FUNC (orc, andc)
-FUSED_FUNC (xor, andc)
-
-FUSED_FUNC (and, eqv)
-FUSED_FUNC (andc, eqv)
-FUSED_FUNC (eqv, eqv)
-FUSED_FUNC (nand, eqv)
-FUSED_FUNC (nor, eqv)
-FUSED_FUNC (or, eqv)
-FUSED_FUNC (orc, eqv)
-FUSED_FUNC (xor, eqv)
-
-FUSED_FUNC (and, nand)
-FUSED_FUNC (andc, nand)
-FUSED_FUNC (eqv, nand)
-FUSED_FUNC (nand, nand)
-FUSED_FUNC (nor, nand)
-FUSED_FUNC (or, nand)
-FUSED_FUNC (orc, nand)
-FUSED_FUNC (xor, nand)
-
-FUSED_FUNC (and, nor)
-FUSED_FUNC (andc, nor)
-FUSED_FUNC (eqv, nor)
-FUSED_FUNC (nand, nor)
-FUSED_FUNC (nor, nor)
-FUSED_FUNC (or, nor)
-FUSED_FUNC (orc, nor)
-FUSED_FUNC (xor, nor)
-
-FUSED_FUNC (and, or)
-FUSED_FUNC (andc, or)
-FUSED_FUNC (eqv, or)
-FUSED_FUNC (nand, or)
-FUSED_FUNC (nor, or)
-FUSED_FUNC (or, or)
-FUSED_FUNC (orc, or)
-FUSED_FUNC (xor, or)
-
-FUSED_FUNC (and, orc)
-FUSED_FUNC (andc, orc)
-FUSED_FUNC (eqv, orc)
-FUSED_FUNC (nand, orc)
-FUSED_FUNC (nor, orc)
-FUSED_FUNC (or, orc)
-FUSED_FUNC (orc, orc)
-FUSED_FUNC (xor, orc)
-
-FUSED_FUNC (and, xor)
-FUSED_FUNC (andc, xor)
-FUSED_FUNC (eqv, xor)
-FUSED_FUNC (nand, xor)
-FUSED_FUNC (nor, xor)
-FUSED_FUNC (or, xor)
-FUSED_FUNC (orc, xor)
-FUSED_FUNC (xor, xor)
-
-
-/* List of functions to check. */
-typedef void func_t (vector_t,
- vector_t,
- vector_t);
-
-typedef func_t *ptr_func_t;
-
-static ptr_func_t functions[] = {
- and_and,
- andc_and,
- eqv_and,
- nand_and,
- nor_and,
- or_and,
- orc_and,
- xor_and,
-
- and_andc,
- andc_andc,
- eqv_andc,
- nand_andc,
- nor_andc,
- or_andc,
- orc_andc,
- xor_andc,
-
- and_eqv,
- andc_eqv,
- eqv_eqv,
- nand_eqv,
- nor_eqv,
- or_eqv,
- orc_eqv,
- xor_eqv,
-
- and_nand,
- andc_nand,
- eqv_nand,
- nand_nand,
- nor_nand,
- or_nand,
- orc_nand,
- xor_nand,
-
- and_nor,
- andc_nor,
- eqv_nor,
- nand_nor,
- nor_nor,
- or_nor,
- orc_nor,
- xor_nor,
-
- and_or,
- andc_or,
- eqv_or,
- nand_or,
- nor_or,
- or_or,
- orc_or,
- xor_or,
-
- and_orc,
- andc_orc,
- eqv_orc,
- nand_orc,
- nor_orc,
- or_orc,
- orc_orc,
- xor_orc,
-
- and_xor,
- andc_xor,
- eqv_xor,
- nand_xor,
- nor_xor,
- or_xor,
- orc_xor,
- xor_xor,
-};
-
-
-int
-main (void)
-{
- scalar_t s_a = 0x0fu;
- scalar_t s_b = 0xaau;
- scalar_t s_c = 0xccu;
-
- vector_t a = (vector_t) { s_a, s_a, ~s_a, ~s_a };
- vector_t b = (vector_t) { s_b, ~s_b, s_b, ~s_b };
- vector_t c = (vector_t) { s_c, ~s_c, ~s_c, s_c };
-
- size_t i;
-
- for (i = 0; i < sizeof (functions) / sizeof (functions[0]); i++)
- functions[i] (a, b, c);
-
-#ifdef DEBUG
- printf ("Done, %d tests, %d failures\n", tests, errors);
- return errors;
-
-#else
- return 0;
-#endif
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-2.c
b/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-2.c
deleted file mode 100644
index f074622c9f67..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/p10-vector-fused-2.c
+++ /dev/null
@@ -1,936 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Make sure all of the fusion cases that generate the xxeval instruction
- actually generate it. */
-typedef vector unsigned int vector_t;
-
-static inline vector_t
-vector_and (vector_t x, vector_t y)
-{
- return x & y;
-}
-
-static inline vector_t
-vector_or (vector_t x, vector_t y)
-{
- return x | y;
-}
-
-static inline vector_t
-vector_xor (vector_t x, vector_t y)
-{
- return x ^ y;
-}
-
-static inline vector_t
-vector_andc (vector_t x, vector_t y)
-{
- return x & ~y;
-}
-
-static inline vector_t
-vector_orc (vector_t x, vector_t y)
-{
- return x | ~y;
-}
-
-static inline vector_t
-vector_nand (vector_t x, vector_t y)
-{
- return ~(x & y);
-}
-
-static inline vector_t
-vector_nor (vector_t x, vector_t y)
-{
- return ~(x | y);
-}
-
-static inline vector_t
-vector_eqv (vector_t x, vector_t y)
-{
- return ~(x ^ y);
-}
-
-void
-and_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,1. */
- r = vector_and (a, vector_and (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-and_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,14. */
- r = vector_andc (a, vector_and (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-and_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,31. */
- r = vector_or (a, vector_and (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-and_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,239. */
- r = vector_orc (a, vector_and (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-and_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,30. */
- r = vector_xor (a, vector_and (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-andc_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,14. */
- r = vector_andc (a, vector_and (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-andc_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,11. */
- r = vector_andc (a, vector_andc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-andc_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,210. */
- r = vector_eqv (a, vector_andc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-andc_nand (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,239. */
- r = vector_nand (a, vector_andc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-andc_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,47. */
- r = vector_or (a, vector_andc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-andc_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,191. */
- r = vector_orc (a, vector_andc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-andc_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,45. */
- r = vector_xor (a, vector_andc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-eqv_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,9. */
- r = vector_and (a, vector_eqv (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-eqv_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,210. */
- r = vector_eqv (a, vector_andc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-eqv_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,105. */
- r = vector_eqv (a, vector_eqv (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-eqv_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,159. */
- r = vector_or (a, vector_eqv (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-eqv_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,111. */
- r = vector_orc (a, vector_eqv (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nand_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,14. */
- r = vector_and (a, vector_nand (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nand_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,1. */
- r = vector_andc (a, vector_nand (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nand_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,30. */
- r = vector_eqv (a, vector_nand (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nand_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,2. */
- r = vector_nor (a, vector_nand (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nand_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,31. */
- r = vector_orc (a, vector_nand (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nor_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,8. */
- r = vector_and (a, vector_nor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nor_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,7. */
- r = vector_andc (a, vector_nor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nor_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,120. */
- r = vector_eqv (a, vector_nor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nor_nand (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,191. */
- r = vector_nand (a, vector_nor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nor_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,143. */
- r = vector_or (a, vector_nor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-nor_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,127. */
- r = vector_orc (a, vector_nor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-or_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,7. */
- r = vector_and (a, vector_or (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-or_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,8. */
- r = vector_andc (a, vector_or (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-or_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,127. */
- r = vector_or (a, vector_or (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-or_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,143. */
- r = vector_orc (a, vector_or (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-or_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,120. */
- r = vector_xor (a, vector_or (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-orc_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,11. */
- r = vector_and (a, vector_orc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-orc_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,2. */
- r = vector_andc (a, vector_orc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-orc_eqv (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,75. */
- r = vector_eqv (a, vector_orc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-orc_nor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,8. */
- r = vector_nor (a, vector_orc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-orc_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,191. */
- r = vector_or (a, vector_orc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-orc_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,47. */
- r = vector_orc (a, vector_orc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-orc_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,180. */
- r = vector_xor (a, vector_orc (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-xor_and (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,6. */
- r = vector_and (a, vector_xor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-xor_andc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,9. */
- r = vector_andc (a, vector_xor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-xor_nand (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,249. */
- r = vector_nand (a, vector_xor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-xor_or (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,111. */
- r = vector_or (a, vector_xor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-xor_orc (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,159. */
- r = vector_orc (a, vector_xor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-void
-xor_xor (vector_t *p_a, vector_t *p_b, vector_t *p_c, vector_t *p_r)
-{
- vector_t a = *p_a;
- vector_t b = *p_b;
- vector_t c = *p_c;
- vector_t r;
-
- __asm__ (" # force fpr registers, %x0,%x1,%x2"
- : "+d" (a), "+d" (b), "+d" (c));
-
- /* xxeval r,a,b,c,105. */
- r = vector_xor (a, vector_xor (b, c));
-
- __asm__ (" # force fpr result, %x0" : "+d" (r));
- *p_r = r;
- return;
-}
-
-/* Make sure none of traditional logical instructions are generated. Skip
- checking for xxlor in case the register allocator decides to add some vector
- moves. */
-/* { dg-final { scan-assembler-not {\mv(and|or|xor|andc|orc|nand|nor|eqv)\M}
} } */
-/* { dg-final { scan-assembler-not {\mxxl(and|xor|andc|orc|nand|nor|eqv)\M}
} } */
-/* { dg-final { scan-assembler-times {\mxxeval\M} 46 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
deleted file mode 100644
index 5a5f37755077..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the xvrl (vector word rotate left using VSX registers insead of
- Altivec registers is generated. */
-
-#include <altivec.h>
-
-typedef vector unsigned int v4si_t;
-
-v4si_t
-rotl_v4si_scalar (v4si_t x, unsigned long n)
-{
- __asm__ (" # %x0" : "+f" (x));
- return (x << n) | (x >> (32 - n)); /* xvrlw. */
-}
-
-v4si_t
-rotr_v4si_scalar (v4si_t x, unsigned long n)
-{
- __asm__ (" # %x0" : "+f" (x));
- return (x >> n) | (x << (32 - n)); /* xvrlw. */
-}
-
-v4si_t
-rotl_v4si_vector (v4si_t x, v4si_t y)
-{
- __asm__ (" # %x0" : "+f" (x)); /* xvrlw. */
- return vec_rl (x, y);
-}
-
-/* { dg-final { scan-assembler-times {\mxvrlw\M} 3 } } */
