https://gcc.gnu.org/g:403e361d5aa620e77c9832578b2409a0fdd79d96
commit r15-4566-g403e361d5aa620e77c9832578b2409a0fdd79d96
Author: liuhongt <hongtao....@intel.com>
Date: Tue Oct 22 01:54:40 2024 -0700
Fix ICE due to isa mismatch for the builtins.
gcc/ChangeLog:
PR target/117240
* config/i386/i386-builtin.def: Add avx/avx512f to vaes
ymm/zmm builtins.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr117240_avx.c: New test.
* gcc.target/i386/pr117240_avx512f.c: New test.
Diff:
---
gcc/config/i386/i386-builtin.def | 16 ++++++++--------
gcc/testsuite/gcc.target/i386/pr117240_avx.c | 10 ++++++++++
gcc/testsuite/gcc.target/i386/pr117240_avx512f.c | 10 ++++++++++
3 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 151ccf4f252a..1eb631db7109 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -2819,17 +2819,17 @@ BDESC (0, OPTION_MASK_ISA2_RDPID, CODE_FOR_rdpid,
"__builtin_ia32_rdpid", IX86_B
/* VAES. */
BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES,
CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
-BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi,
"__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int)
V32QI_FTYPE_V32QI_V32QI)
-BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512,
CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64,
UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
+BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi,
"__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int)
V32QI_FTYPE_V32QI_V32QI)
+BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES |
OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdec_v64qi,
"__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int)
V64QI_FTYPE_V64QI_V64QI)
BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES,
CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi",
IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
-BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi,
"__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int)
V32QI_FTYPE_V32QI_V32QI)
-BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512,
CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi",
IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
+BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi,
"__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int)
V32QI_FTYPE_V32QI_V32QI)
+BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES |
OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesdeclast_v64qi,
"__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int)
V64QI_FTYPE_V64QI_V64QI)
BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES,
CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
-BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi,
"__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int)
V32QI_FTYPE_V32QI_V32QI)
-BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512,
CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64,
UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
+BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi,
"__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int)
V32QI_FTYPE_V32QI_V32QI)
+BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES |
OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenc_v64qi,
"__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int)
V64QI_FTYPE_V64QI_V64QI)
BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES,
CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi",
IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
-BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi,
"__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int)
V32QI_FTYPE_V32QI_V32QI)
-BDESC (0, OPTION_MASK_ISA2_VAES | OPTION_MASK_ISA2_EVEX512,
CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi",
IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
+BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi,
"__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int)
V32QI_FTYPE_V32QI_V32QI)
+BDESC (OPTION_MASK_ISA_AVX512F, OPTION_MASK_ISA2_VAES |
OPTION_MASK_ISA2_EVEX512, CODE_FOR_vaesenclast_v64qi,
"__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int)
V64QI_FTYPE_V64QI_V64QI)
/* BF16 */
BDESC (0, OPTION_MASK_ISA2_AVX512BF16 | OPTION_MASK_ISA2_EVEX512,
CODE_FOR_avx512f_cvtne2ps2bf16_v32bf, "__builtin_ia32_cvtne2ps2bf16_v32bf",
IX86_BUILTIN_CVTNE2PS2BF16_V32BF, UNKNOWN, (int) V32BF_FTYPE_V16SF_V16SF)
diff --git a/gcc/testsuite/gcc.target/i386/pr117240_avx.c
b/gcc/testsuite/gcc.target/i386/pr117240_avx.c
new file mode 100644
index 000000000000..88e83085315a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr117240_avx.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mvaes -mno-xsave -Wno-psabi" } */
+
+typedef __attribute__((__vector_size__(32))) char V;
+
+V
+foo(V v)
+{
+ return __builtin_ia32_vaesenc_v32qi(v, v);/* { dg-error "needs isa option" }
*/
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c
b/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c
new file mode 100644
index 000000000000..c2d616a05e37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mvaes -mevex512 -mno-xsave -Wno-psabi" } */
+
+typedef __attribute__((__vector_size__(64))) char V;
+
+V
+foo(V v)
+{
+ return __builtin_ia32_vaesenc_v64qi(v, v);/* { dg-error "needs isa option" }
*/
+}
