https://gcc.gnu.org/g:e1762af3056f0491d0c2a7d14dcd86d425c4a92e
commit r15-4426-ge1762af3056f0491d0c2a7d14dcd86d425c4a92e
Author: Christophe Lyon <christophe.l...@linaro.org>
Date: Wed Jul 10 21:52:46 2024 +0000
arm: [MVE intrinsics] factorize vcvtq
Factorize vcvtq so that they use parameterized names.
2024-07-11 Christophe Lyon <christophe.l...@linaro.org>
gcc/
* config/arm/iterators.md (mve_insn): Add VCVTQ_FROM_F_S,
VCVTQ_FROM_F_U, VCVTQ_M_FROM_F_S, VCVTQ_M_FROM_F_U,
VCVTQ_M_N_FROM_F_S, VCVTQ_M_N_FROM_F_U, VCVTQ_M_N_TO_F_S,
VCVTQ_M_N_TO_F_U, VCVTQ_M_TO_F_S, VCVTQ_M_TO_F_U,
VCVTQ_N_FROM_F_S, VCVTQ_N_FROM_F_U, VCVTQ_N_TO_F_S,
VCVTQ_N_TO_F_U, VCVTQ_TO_F_S, VCVTQ_TO_F_U.
* config/arm/mve.md (mve_vcvtq_to_f_<supf><mode>): Rename into
@mve_<mve_insn>q_to_f_<supf><mode>.
(mve_vcvtq_from_f_<supf><mode>): Rename into
@mve_<mve_insn>q_from_f_<supf><mode>.
(mve_vcvtq_n_to_f_<supf><mode>): Rename into
@mve_<mve_insn>q_n_to_f_<supf><mode>.
(mve_vcvtq_n_from_f_<supf><mode>): Rename into
@mve_<mve_insn>q_n_from_f_<supf><mode>.
(mve_vcvtq_m_to_f_<supf><mode>): Rename into
@mve_<mve_insn>q_m_to_f_<supf><mode>.
(mve_vcvtq_m_n_from_f_<supf><mode>): Rename into
@mve_<mve_insn>q_m_n_from_f_<supf><mode>.
(mve_vcvtq_m_from_f_<supf><mode>): Rename into
@mve_<mve_insn>q_m_from_f_<supf><mode>.
(mve_vcvtq_m_n_to_f_<supf><mode>): Rename into
@mve_<mve_insn>q_m_n_to_f_<supf><mode>.
Diff:
---
gcc/config/arm/iterators.md | 8 ++++++
gcc/config/arm/mve.md | 64 ++++++++++++++++++++++-----------------------
2 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index b9ff01cb104e..bf800625face 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -964,6 +964,14 @@
(VCMLAQ_M_F "vcmla") (VCMLAQ_ROT90_M_F "vcmla")
(VCMLAQ_ROT180_M_F "vcmla") (VCMLAQ_ROT270_M_F "vcmla")
(VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul")
(VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul")
(VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F
"vcreate")
+ (VCVTQ_FROM_F_S "vcvt") (VCVTQ_FROM_F_U "vcvt")
+ (VCVTQ_M_FROM_F_S "vcvt") (VCVTQ_M_FROM_F_U "vcvt")
+ (VCVTQ_M_N_FROM_F_S "vcvt") (VCVTQ_M_N_FROM_F_U "vcvt")
+ (VCVTQ_M_N_TO_F_S "vcvt") (VCVTQ_M_N_TO_F_U "vcvt")
+ (VCVTQ_M_TO_F_S "vcvt") (VCVTQ_M_TO_F_U "vcvt")
+ (VCVTQ_N_FROM_F_S "vcvt") (VCVTQ_N_FROM_F_U "vcvt")
+ (VCVTQ_N_TO_F_S "vcvt") (VCVTQ_N_TO_F_U "vcvt")
+ (VCVTQ_TO_F_S "vcvt") (VCVTQ_TO_F_U "vcvt")
(VDUPQ_M_N_S "vdup") (VDUPQ_M_N_U "vdup") (VDUPQ_M_N_F "vdup")
(VDUPQ_N_S "vdup") (VDUPQ_N_U "vdup") (VDUPQ_N_F "vdup")
(VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 7ace8b1c8085..686620035a8d 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -236,17 +236,17 @@
])
;;
-;; [vcvtq_to_f_s, vcvtq_to_f_u])
+;; [vcvtq_to_f_s, vcvtq_to_f_u]
;;
-(define_insn "mve_vcvtq_to_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_to_f_<supf><mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
VCVTQ_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
- [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_vcvtq_to_f_<supf><mode>"))
+ "<mve_insn>.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_<mve_insn>q_to_f_<supf><mode>"))
(set_attr "type" "mve_move")
])
@@ -266,17 +266,17 @@
])
;;
-;; [vcvtq_from_f_s, vcvtq_from_f_u])
+;; [vcvtq_from_f_s, vcvtq_from_f_u]
;;
-(define_insn "mve_vcvtq_from_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_from_f_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
VCVTQ_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
- [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_vcvtq_from_f_<supf><mode>"))
+ "<mve_insn>.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_<mve_insn>q_from_f_<supf><mode>"))
(set_attr "type" "mve_move")
])
@@ -554,9 +554,9 @@
])
;;
-;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
+;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u]
;;
-(define_insn "mve_vcvtq_n_to_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_to_f_<supf><mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
@@ -564,8 +564,8 @@
VCVTQ_N_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_vcvtq_n_to_f_<supf><mode>"))
+ "<mve_insn>.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_<mve_insn>q_n_to_f_<supf><mode>"))
(set_attr "type" "mve_move")
])
@@ -652,9 +652,9 @@
])
;;
-;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
+;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]
;;
-(define_insn "mve_vcvtq_n_from_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_from_f_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
@@ -662,8 +662,8 @@
VCVTQ_N_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_vcvtq_n_from_f_<supf><mode>"))
+ "<mve_insn>.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_<mve_insn>q_n_from_f_<supf><mode>"))
(set_attr "type" "mve_move")
])
@@ -1645,9 +1645,9 @@
(set_attr "length""8")])
;;
-;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
+;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]
;;
-(define_insn "mve_vcvtq_m_to_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_to_f_<supf><mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
@@ -1656,8 +1656,8 @@
VCVTQ_M_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_vcvtq_to_f_<supf><mode>"))
+ "vpst\;<mve_insn>t.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_<mve_insn>q_to_f_<supf><mode>"))
(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -2624,9 +2624,9 @@
(set_attr "length""8")])
;;
-;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
+;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u]
;;
-(define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_from_f_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
@@ -2636,8 +2636,8 @@
VCVTQ_M_N_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
- [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_vcvtq_n_from_f_<supf><mode>"))
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_<mve_insn>q_n_from_f_<supf><mode>"))
(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -2659,9 +2659,9 @@
(set_attr "length""8")])
;;
-;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
+;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s]
;;
-(define_insn "mve_vcvtq_m_from_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_from_f_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
@@ -2670,8 +2670,8 @@
VCVTQ_M_FROM_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
- [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_vcvtq_from_f_<supf><mode>"))
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_<mve_insn>q_from_f_<supf><mode>"))
(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -2730,9 +2730,9 @@
(set_attr "length" "8")])
;;
-;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
+;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]
;;
-(define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_to_f_<supf><mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
@@ -2742,8 +2742,8 @@
VCVTQ_M_N_TO_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
- [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_vcvtq_n_to_f_<supf><mode>"))
+ "vpst\;<mve_insn>t.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set (attr "mve_unpredicated_insn") (symbol_ref
"CODE_FOR_mve_<mve_insn>q_n_to_f_<supf><mode>"))
(set_attr "type" "mve_move")
(set_attr "length""8")])
