https://gcc.gnu.org/g:2a47025f4bd01f97a215a3f501a3c56871702a0c
commit 2a47025f4bd01f97a215a3f501a3c56871702a0c
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Oct 2 13:58:10 2024 -0400
Add vector-pair.h tests.
2024-10-02 Michael Meissner <meiss...@linux.ibm.com>
gcc/testsuite
* gcc.target/powerpc/vpair-1.c: New test.
* gcc.target/powerpc/vpair-2.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vpair-1.c | 141 +++++++++++++++++++++++++++++
gcc/testsuite/gcc.target/powerpc/vpair-2.c | 141 +++++++++++++++++++++++++++++
2 files changed, 282 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/vpair-1.c
b/gcc/testsuite/gcc.target/powerpc/vpair-1.c
new file mode 100644
index 000000000000..55772cc44e31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vpair-1.c
@@ -0,0 +1,141 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+/* Test whether the vector builtin code generates the expected instructions for
+ vector pairs with 4 double elements. */
+
+#include <vector-pair.h>
+
+void
+test_add (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x,
+ vector_pair_f64_t *y)
+{
+ /* 2 lxvp, 2 xvadddp, 1 stxvp. */
+ vpair_f64_add (dest, x, y);
+}
+
+void
+test_sub (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x,
+ vector_pair_f64_t *y)
+{
+ /* 2 lxvp, 2 xvsubdp, 1 stxvp. */
+ vpair_f64_sub (dest, x, y);
+}
+
+void
+test_multiply (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x,
+ vector_pair_f64_t *y)
+{
+ /* 2 lxvp, 2 xvmuldp, 1 stxvp. */
+ vpair_f64_mul (dest, x, y);
+}
+
+void
+test_min (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x,
+ vector_pair_f64_t *y)
+{
+ /* 2 lxvp, 2 xvmindp, 1 stxvp. */
+ vpair_f64_min (dest, x, y);
+}
+
+void
+test_max (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x,
+ vector_pair_f64_t *y)
+{
+ /* 2 lxvp, 2 xvmaxdp, 1 stxvp. */
+ vpair_f64_max (dest, x, y);
+}
+
+void
+test_negate (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x)
+{
+ /* 1 lxvp, 2 xvnegdp, 1 stxvp. */
+ vpair_f64_neg (dest, x);
+}
+
+void
+test_abs (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x)
+{
+ /* 1 lxvp, 2 xvabsdp, 1 stxvp. */
+ vpair_f64_abs (dest, x);
+}
+
+void
+test_negative_abs (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x)
+{
+ /* 2 lxvp, 2 xvnabsdp, 1 stxvp. */
+ vpair_f64_nabs (dest, x);
+}
+
+void
+test_sqrt (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x)
+{
+ /* 1 lxvp, 2 xvabsdp, 1 stxvp. */
+ vpair_f64_sqrt (dest, x);
+}
+
+void
+test_fma (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x,
+ vector_pair_f64_t *y,
+ vector_pair_f64_t *z)
+{
+ /* 2 lxvp, 2 xvmadd{a,m}dp, 1 stxvp. */
+ vpair_f64_fma (dest, x, y, z);
+}
+
+void
+test_fms (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x,
+ vector_pair_f64_t *y,
+ vector_pair_f64_t *z)
+{
+ /* 2 lxvp, 2 xvmsub{a,m}dp, 1 stxvp. */
+ vpair_f64_fms (dest, x, y, z);
+}
+
+void
+test_nfma (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x,
+ vector_pair_f64_t *y,
+ vector_pair_f64_t *z)
+{
+ /* 2 lxvp, 2 xvnmadd{a,m}dp, 1 stxvp. */
+ vpair_f64_nfma (dest, x, y, z);
+}
+
+void
+test_nfms (vector_pair_f64_t *dest,
+ vector_pair_f64_t *x,
+ vector_pair_f64_t *y,
+ vector_pair_f64_t *z)
+{
+ /* 2 lxvp, 2 xvnmsub{a,m}dp, 1 stxvp. */
+ vpair_f64_nfms (dest, x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mlxvp\M} 26 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */
+/* { dg-final { scan-assembler-times {\mxvabsdp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvadddp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvmadd.dp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvmaxdp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvmindp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvmsub.dp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvmuldp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvnabsdp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvnegdp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvnmadd.dp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvnmsub.dp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvsubdp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vpair-2.c
b/gcc/testsuite/gcc.target/powerpc/vpair-2.c
new file mode 100644
index 000000000000..3030b0b33380
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vpair-2.c
@@ -0,0 +1,141 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+/* Test whether the vector builtin code generates the expected instructions for
+ vector pairs with 4 double elements. */
+
+#include <vector-pair.h>
+
+void
+test_add (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x,
+ vector_pair_f32_t *y)
+{
+ /* 2 lxvp, 2 xvaddsp, 1 stxvp. */
+ vpair_f32_add (dest, x, y);
+}
+
+void
+test_sub (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x,
+ vector_pair_f32_t *y)
+{
+ /* 2 lxvp, 2 xvsubsp, 1 stxvp. */
+ vpair_f32_sub (dest, x, y);
+}
+
+void
+test_multiply (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x,
+ vector_pair_f32_t *y)
+{
+ /* 2 lxvp, 2 xvmulsp, 1 stxvp. */
+ vpair_f32_mul (dest, x, y);
+}
+
+void
+test_min (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x,
+ vector_pair_f32_t *y)
+{
+ /* 2 lxvp, 2 xvminsp, 1 stxvp. */
+ vpair_f32_min (dest, x, y);
+}
+
+void
+test_max (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x,
+ vector_pair_f32_t *y)
+{
+ /* 2 lxvp, 2 xvmaxsp, 1 stxvp. */
+ vpair_f32_max (dest, x, y);
+}
+
+void
+test_negate (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x)
+{
+ /* 1 lxvp, 2 xvnegsp, 1 stxvp. */
+ vpair_f32_neg (dest, x);
+}
+
+void
+test_abs (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x)
+{
+ /* 1 lxvp, 2 xvabssp, 1 stxvp. */
+ vpair_f32_abs (dest, x);
+}
+
+void
+test_negative_abs (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x)
+{
+ /* 2 lxvp, 2 xvnabssp, 1 stxvp. */
+ vpair_f32_nabs (dest, x);
+}
+
+void
+test_sqrt (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x)
+{
+ /* 1 lxvp, 2 xvabssp, 1 stxvp. */
+ vpair_f32_sqrt (dest, x);
+}
+
+void
+test_fma (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x,
+ vector_pair_f32_t *y,
+ vector_pair_f32_t *z)
+{
+ /* 2 lxvp, 2 xvmadd{a,m}sp, 1 stxvp. */
+ vpair_f32_fma (dest, x, y, z);
+}
+
+void
+test_fms (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x,
+ vector_pair_f32_t *y,
+ vector_pair_f32_t *z)
+{
+ /* 2 lxvp, 2 xvmsub{a,m}sp, 1 stxvp. */
+ vpair_f32_fms (dest, x, y, z);
+}
+
+void
+test_nfma (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x,
+ vector_pair_f32_t *y,
+ vector_pair_f32_t *z)
+{
+ /* 2 lxvp, 2 xvnmadd{a,m}sp, 1 stxvp. */
+ vpair_f32_nfma (dest, x, y, z);
+}
+
+void
+test_nfms (vector_pair_f32_t *dest,
+ vector_pair_f32_t *x,
+ vector_pair_f32_t *y,
+ vector_pair_f32_t *z)
+{
+ /* 2 lxvp, 2 xvnmsub{a,m}sp, 1 stxvp. */
+ vpair_f32_nfms (dest, x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mlxvp\M} 26 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 13 } } */
+/* { dg-final { scan-assembler-times {\mxvabssp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvaddsp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvmadd.sp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvmaxsp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvminsp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvmsub.sp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvmulsp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvnabssp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvnegsp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvnmadd.sp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvnmsub.sp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvsqrtsp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvsubsp\M} 2 } } */
