[gcc r15-3885] Define VECTOR_STORE_FLAG_VALUE

[hongtao Liu via Gcc-cvs]

https://gcc.gnu.org/g:78eef8919e2f2973ed7750ba66f5726e70614d07

commit r15-3885-g78eef8919e2f2973ed7750ba66f5726e70614d07
Author: liuhongt <hongtao....@intel.com>
Date:   Mon Sep 23 11:06:04 2024 +0800

    Define VECTOR_STORE_FLAG_VALUE
    
    gcc/ChangeLog:
    
            * config/i386/i386.h (VECTOR_STORE_FLAG_VALUE): New macro.
    
    gcc/testsuite/ChangeLog:
            * gcc.dg/rtl/x86_64/vector_eq.c: New test.

Diff:
---
 gcc/config/i386/i386.h                      |  5 ++++-
 gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c | 26 ++++++++++++++++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 751c250ddb31..58e6f2826bf6 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -899,7 +899,10 @@ extern const char *host_detect_local_cpu (int argc, const 
char **argv);
    and give entire struct the alignment of an int.  */
 /* Required on the 386 since it doesn't have bit-field insns.  */
 #define PCC_BITFIELD_TYPE_MATTERS 1
-
+
+#define VECTOR_STORE_FLAG_VALUE(MODE) \
+  (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT ? constm1_rtx : NULL_RTX)
+
 /* Standard register usage.  */
 
 /* This processor has special stack-like registers.  See reg-stack.cc
diff --git a/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c 
b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
new file mode 100644
index 000000000000..6704c28e586e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && lp64 } } } */
+/* { dg-additional-options "-O2 -march=x86-64-v3" } */
+
+typedef int v4si __attribute__((vector_size(16)));
+
+v4si __RTL (startwith ("vregs")) foo (void)
+{
+(function "foo"
+  (insn-chain
+    (block 2
+      (edge-from entry (flags "FALLTHRU"))
+      (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK)
+      (cnote 2 NOTE_INSN_FUNCTION_BEG)
+      (cinsn 3 (set (reg:V4SI <0>) (const_vector:V4SI [(const_int 0) 
(const_int 0) (const_int 0) (const_int 0)])))
+      (cinsn 5 (set (reg:V4SI <2>)
+                   (eq:V4SI (reg:V4SI <0>) (reg:V4SI <1>))))
+      (cinsn 6 (set (reg:V4SI <3>) (reg:V4SI <2>)))
+      (cinsn 7 (set (reg:V4SI xmm0) (reg:V4SI <3>)))
+      (edge-to exit (flags "FALLTHRU"))
+    )
+  )
+ (crtl (return_rtx (reg/i:V4SI xmm0)))
+)
+}
+
+/* { dg-final { scan-assembler-not "vpxor" } } */