https://gcc.gnu.org/g:f4f2d6dd3d73321f177b2f9926a41bcd2e3a3300
commit r13-9051-gf4f2d6dd3d73321f177b2f9926a41bcd2e3a3300
Author: John David Anglin <dang...@gcc.gnu.org>
Date: Wed Sep 18 11:02:32 2024 -0400
hppa: Add peephole2 optimizations for REG+D loads and stores
The PA 1.x architecture only supports long displacements in
integer loads and stores. Floating-point loads and stores
only support short displacements. As a result, we have to
wait until reload is complete before generating insns with
long displacements.
The PA 2.0 architecture supports long displacements in both
integer and floating-point loads and stores.
The peephole2 optimizations added in this change are only
enabled when 14-bit long displacements aren't supported for
floating-point loads and stores.
2024-09-18 John David Anglin <dang...@gcc.gnu.org>
gcc/ChangeLog:
* config/pa/pa.h (GENERAL_REGNO_P): Define.
* config/pa/pa.md: Add SImode and SFmode peephole2
patterns to generate loads and stores with long
displacements.
Diff:
---
gcc/config/pa/pa.h | 3 ++
gcc/config/pa/pa.md | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 103 insertions(+)
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 6e29be282ad9..2e8b248c2fcc 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -475,6 +475,9 @@ extern rtx hppa_pic_save_rtx (void);
#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS GENERAL_REGS
+/* True if register is a general register. */
+#define GENERAL_REGNO_P(N) ((N) >= 1 && (N) <= 31)
+
#define FP_REG_CLASS_P(CLASS) \
((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index d832a29683c2..c01719467856 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2270,6 +2270,58 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
+; Rewrite RTL using a REG+D store. This will allow the insn that
+; computes the address to be deleted if the register it sets is dead.
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))
+ (set (mem:SI (match_dup 0))
+ (match_operand:SI 3 "register_operand" ""))]
+ "!TARGET_64BIT
+ && !INT14_OK_STRICT
+ && GENERAL_REGNO_P (REGNO (operands[0]))
+ && GENERAL_REGNO_P (REGNO (operands[3]))
+ && REGNO (operands[0]) != REGNO (operands[3])
+ && base14_operand (operands[2], E_SImode)"
+ [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3))
+ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+ "")
+
+; Rewrite RTL using a REG+D load. This will allow the insn that
+; computes the address to be deleted if the register it sets is dead.
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))
+ (set (match_operand:SI 3 "register_operand" "")
+ (mem:SI (match_dup 0)))]
+ "!TARGET_64BIT
+ && !INT14_OK_STRICT
+ && GENERAL_REGNO_P (REGNO (operands[0]))
+ && GENERAL_REGNO_P (REGNO (operands[3]))
+ && REGNO (operands[0]) != REGNO (operands[3])
+ && REGNO (operands[1]) != REGNO (operands[3])
+ && base14_operand (operands[2], E_SImode)"
+ [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+ "")
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))
+ (set (match_operand:SI 3 "register_operand" "")
+ (mem:SI (match_dup 0)))]
+ "!TARGET_64BIT
+ && !INT14_OK_STRICT
+ && GENERAL_REGNO_P (REGNO (operands[0]))
+ && GENERAL_REGNO_P (REGNO (operands[3]))
+ && REGNO (operands[0]) == REGNO (operands[3])
+ && base14_operand (operands[2], E_SImode)"
+ [(set (match_dup 3) (mem:SI (plus:SI (match_dup 1) (match_dup 2))))]
+ "")
+
; Rewrite RTL using an indexed store. This will allow the insn that
; computes the address to be deleted if the register it sets is dead.
(define_peephole2
@@ -4497,6 +4549,54 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4")])
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))
+ (set (mem:SF (match_dup 0))
+ (match_operand:SF 3 "register_operand" ""))]
+ "!TARGET_64BIT
+ && !INT14_OK_STRICT
+ && GENERAL_REGNO_P (REGNO (operands[0]))
+ && GENERAL_REGNO_P (REGNO (operands[3]))
+ && REGNO (operands[0]) != REGNO (operands[3])
+ && base14_operand (operands[2], E_SImode)"
+ [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2))) (match_dup 3))
+ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+ "")
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))
+ (set (match_operand:SF 3 "register_operand" "")
+ (mem:SF (match_dup 0)))]
+ "!TARGET_64BIT
+ && !INT14_OK_STRICT
+ && GENERAL_REGNO_P (REGNO (operands[0]))
+ && GENERAL_REGNO_P (REGNO (operands[3]))
+ && REGNO (operands[0]) != REGNO (operands[3])
+ && REGNO (operands[1]) != REGNO (operands[3])
+ && base14_operand (operands[2], E_SImode)"
+ [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2))))
+ (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
+ "")
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))
+ (set (match_operand:SF 3 "register_operand" "")
+ (mem:SF (match_dup 0)))]
+ "!TARGET_64BIT
+ && !INT14_OK_STRICT
+ && GENERAL_REGNO_P (REGNO (operands[0]))
+ && GENERAL_REGNO_P (REGNO (operands[3]))
+ && REGNO (operands[0]) == REGNO (operands[3])
+ && base14_operand (operands[2], E_SImode)"
+ [(set (match_dup 3) (mem:SF (plus:DI (match_dup 1) (match_dup 2))))]
+ "")
+
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
