https://gcc.gnu.org/g:4af196b2ebd662c5183f1998b0184985e85479b2
commit r15-3666-g4af196b2ebd662c5183f1998b0184985e85479b2
Author: Soumya AR <soum...@nvidia.com>
Date: Tue Sep 10 14:18:44 2024 +0530
aarch64: Emit ADD X, Y, Y instead of SHL X, Y, #1 for SVE instructions.
On Neoverse V2, SVE ADD instructions have a throughput of 4, while shift
instructions like SHL have a throughput of 2. We can lean on that to emit
code
like:
add z31.b, z31.b, z31.b
instead of:
lsl z31.b, z31.b, #1
The implementation of this change for SVE vectors is similar to a prior
patch
<https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659958.html> that
adds
the above functionality for Neon vectors.
Here, the machine descriptor pattern is split up to separately accommodate
left
and right shifts, so we can specifically emit an add for all left shifts by
1.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no
regression.
OK for mainline?
Signed-off-by: Soumya AR <soum...@nvidia.com>
gcc/ChangeLog:
* config/aarch64/aarch64-sve.md (*post_ra_v<optab><mode>3): Split
pattern
to accomodate left and right shifts separately.
(*post_ra_v_ashl<mode>3): Matches left shifts with additional
constraint to check for shifts by 1.
(*post_ra_v_<optab><mode>3): Matches right shifts.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/acle/asm/lsl_s16.c: Updated instances of
lsl-1
with corresponding add.
* gcc.target/aarch64/sve/acle/asm/lsl_s32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_s64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_s8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_u16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_u32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_u64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_u8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c: Likewise.
* gcc.target/aarch64/sve/adr_1.c: Likewise.
* gcc.target/aarch64/sve/adr_6.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_7.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_8.c: Likewise.
* gcc.target/aarch64/sve/shift_2.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_s64.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_u64.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_s64.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_u64.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/rshl_s16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/rshl_s32.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/rshl_s64.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/rshl_s8.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/rshl_u16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/rshl_u32.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/rshl_u64.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/rshl_u8.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_s64.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_u64.c: Likewise.
* gcc.target/aarch64/sve/sve_shl_add.c: New test.
Diff:
---
gcc/config/aarch64/aarch64-sve.md | 18 +++++++--
.../gcc.target/aarch64/sve/acle/asm/lsl_s16.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_s32.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_s64.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_s8.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_u16.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_u32.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_u64.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_u8.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c | 4 +-
.../gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c | 4 +-
gcc/testsuite/gcc.target/aarch64/sve/adr_1.c | 6 +--
gcc/testsuite/gcc.target/aarch64/sve/adr_6.c | 4 +-
gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7.c | 8 ++--
gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8.c | 8 ++--
gcc/testsuite/gcc.target/aarch64/sve/shift_2.c | 6 +--
gcc/testsuite/gcc.target/aarch64/sve/sve_shl_add.c | 45 ++++++++++++++++++++++
.../aarch64/sve2/acle/asm/ldnt1sh_gather_s64.c | 12 +++---
.../aarch64/sve2/acle/asm/ldnt1sh_gather_u64.c | 12 +++---
.../aarch64/sve2/acle/asm/ldnt1uh_gather_s64.c | 12 +++---
.../aarch64/sve2/acle/asm/ldnt1uh_gather_u64.c | 12 +++---
.../gcc.target/aarch64/sve2/acle/asm/rshl_s16.c | 4 +-
.../gcc.target/aarch64/sve2/acle/asm/rshl_s32.c | 4 +-
.../gcc.target/aarch64/sve2/acle/asm/rshl_s64.c | 4 +-
.../gcc.target/aarch64/sve2/acle/asm/rshl_s8.c | 4 +-
.../gcc.target/aarch64/sve2/acle/asm/rshl_u16.c | 4 +-
.../gcc.target/aarch64/sve2/acle/asm/rshl_u32.c | 4 +-
.../gcc.target/aarch64/sve2/acle/asm/rshl_u64.c | 4 +-
.../gcc.target/aarch64/sve2/acle/asm/rshl_u8.c | 4 +-
.../aarch64/sve2/acle/asm/stnt1h_scatter_s64.c | 8 ++--
.../aarch64/sve2/acle/asm/stnt1h_scatter_u64.c | 8 ++--
35 files changed, 151 insertions(+), 96 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve.md
b/gcc/config/aarch64/aarch64-sve.md
index a5cd42be9d5c..bfa28849adf8 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -4816,11 +4816,23 @@
;; Unpredicated shift operations by a constant (post-RA only).
;; These are generated by splitting a predicated instruction whose
;; predicate is unused.
-(define_insn "*post_ra_v<optab><mode>3"
+(define_insn "*post_ra_v_ashl<mode>3"
+ [(set (match_operand:SVE_I 0 "register_operand")
+ (ashift:SVE_I
+ (match_operand:SVE_I 1 "register_operand")
+ (match_operand:SVE_I 2 "aarch64_simd_lshift_imm")))]
+ "TARGET_SVE && reload_completed"
+ {@ [ cons: =0 , 1 , 2 ]
+ [ w , w , vs1 ] add\t%0.<Vetype>, %1.<Vetype>, %1.<Vetype>
+ [ w , w , Dl ] lsl\t%0.<Vetype>, %1.<Vetype>, #%2
+ }
+)
+
+(define_insn "*post_ra_v_<optab><mode>3"
[(set (match_operand:SVE_I 0 "register_operand" "=w")
- (ASHIFT:SVE_I
+ (SHIFTRT:SVE_I
(match_operand:SVE_I 1 "register_operand" "w")
- (match_operand:SVE_I 2 "aarch64_simd_<lr>shift_imm")))]
+ (match_operand:SVE_I 2 "aarch64_simd_rshift_imm")))]
"TARGET_SVE && reload_completed"
"<shift>\t%0.<Vetype>, %1.<Vetype>, #%2"
)
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c
index d5c5fd54e791..710d6f6fc7e8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_s16_x_untied, svint16_t, uint16_t,
/*
** lsl_1_s16_x_tied1:
-** lsl z0\.h, z0\.h, #1
+** add z0\.h, z0\.h, z0\.h
** ret
*/
TEST_UNIFORM_Z (lsl_1_s16_x_tied1, svint16_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_s16_x_tied1, svint16_t,
/*
** lsl_1_s16_x_untied:
-** lsl z0\.h, z1\.h, #1
+** add z0\.h, z1\.h, z1\.h
** ret
*/
TEST_UNIFORM_Z (lsl_1_s16_x_untied, svint16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s32.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s32.c
index b5df8a843188..5ae79ac89974 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s32.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_s32_x_untied, svint32_t, uint32_t,
/*
** lsl_1_s32_x_tied1:
-** lsl z0\.s, z0\.s, #1
+** add z0\.s, z0\.s, z0\.s
** ret
*/
TEST_UNIFORM_Z (lsl_1_s32_x_tied1, svint32_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_s32_x_tied1, svint32_t,
/*
** lsl_1_s32_x_untied:
-** lsl z0\.s, z1\.s, #1
+** add z0\.s, z1\.s, z1\.s
** ret
*/
TEST_UNIFORM_Z (lsl_1_s32_x_untied, svint32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s64.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s64.c
index 850a798fe1f8..fd930daeef42 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s64.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_x0_s64_x_untied, svint64_t, uint64_t,
/*
** lsl_1_s64_x_tied1:
-** lsl z0\.d, z0\.d, #1
+** add z0\.d, z0\.d, z0\.d
** ret
*/
TEST_UNIFORM_Z (lsl_1_s64_x_tied1, svint64_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_s64_x_tied1, svint64_t,
/*
** lsl_1_s64_x_untied:
-** lsl z0\.d, z1\.d, #1
+** add z0\.d, z1\.d, z1\.d
** ret
*/
TEST_UNIFORM_Z (lsl_1_s64_x_untied, svint64_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c
index d8776597129c..e417fb9fa41a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_s8_x_untied, svint8_t, uint8_t,
/*
** lsl_1_s8_x_tied1:
-** lsl z0\.b, z0\.b, #1
+** add z0\.b, z0\.b, z0\.b
** ret
*/
TEST_UNIFORM_Z (lsl_1_s8_x_tied1, svint8_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_s8_x_tied1, svint8_t,
/*
** lsl_1_s8_x_untied:
-** lsl z0\.b, z1\.b, #1
+** add z0\.b, z1\.b, z1\.b
** ret
*/
TEST_UNIFORM_Z (lsl_1_s8_x_untied, svint8_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c
index 068e49b88120..8050fe2beb09 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_u16_x_untied, svuint16_t, uint16_t,
/*
** lsl_1_u16_x_tied1:
-** lsl z0\.h, z0\.h, #1
+** add z0\.h, z0\.h, z0\.h
** ret
*/
TEST_UNIFORM_Z (lsl_1_u16_x_tied1, svuint16_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_u16_x_tied1, svuint16_t,
/*
** lsl_1_u16_x_untied:
-** lsl z0\.h, z1\.h, #1
+** add z0\.h, z1\.h, z1\.h
** ret
*/
TEST_UNIFORM_Z (lsl_1_u16_x_untied, svuint16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u32.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u32.c
index 9c2be1de9675..30968bec630d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u32.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_u32_x_untied, svuint32_t, uint32_t,
/*
** lsl_1_u32_x_tied1:
-** lsl z0\.s, z0\.s, #1
+** add z0\.s, z0\.s, z0\.s
** ret
*/
TEST_UNIFORM_Z (lsl_1_u32_x_tied1, svuint32_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_u32_x_tied1, svuint32_t,
/*
** lsl_1_u32_x_untied:
-** lsl z0\.s, z1\.s, #1
+** add z0\.s, z1\.s, z1\.s
** ret
*/
TEST_UNIFORM_Z (lsl_1_u32_x_untied, svuint32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u64.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u64.c
index 0c1e473ce9d3..2fb97ac61c8e 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u64.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_x0_u64_x_untied, svuint64_t, uint64_t,
/*
** lsl_1_u64_x_tied1:
-** lsl z0\.d, z0\.d, #1
+** add z0\.d, z0\.d, z0\.d
** ret
*/
TEST_UNIFORM_Z (lsl_1_u64_x_tied1, svuint64_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_u64_x_tied1, svuint64_t,
/*
** lsl_1_u64_x_untied:
-** lsl z0\.d, z1\.d, #1
+** add z0\.d, z1\.d, z1\.d
** ret
*/
TEST_UNIFORM_Z (lsl_1_u64_x_untied, svuint64_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c
index 59d386c0f775..636679a854e5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_u8_x_untied, svuint8_t, uint8_t,
/*
** lsl_1_u8_x_tied1:
-** lsl z0\.b, z0\.b, #1
+** add z0\.b, z0\.b, z0\.b
** ret
*/
TEST_UNIFORM_Z (lsl_1_u8_x_tied1, svuint8_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_u8_x_tied1, svuint8_t,
/*
** lsl_1_u8_x_untied:
-** lsl z0\.b, z1\.b, #1
+** add z0\.b, z1\.b, z1\.b
** ret
*/
TEST_UNIFORM_Z (lsl_1_u8_x_untied, svuint8_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c
index 7244f64fb1df..67b652dcbaec 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_s16_x_untied, svint16_t,
uint64_t,
/*
** lsl_wide_1_s16_x_tied1:
-** lsl z0\.h, z0\.h, #1
+** add z0\.h, z0\.h, z0\.h
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_s16_x_tied1, svint16_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_s16_x_tied1, svint16_t,
/*
** lsl_wide_1_s16_x_untied:
-** lsl z0\.h, z1\.h, #1
+** add z0\.h, z1\.h, z1\.h
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_s16_x_untied, svint16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c
index 04333ce477af..77826817dc62 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_s32_x_untied, svint32_t,
uint64_t,
/*
** lsl_wide_1_s32_x_tied1:
-** lsl z0\.s, z0\.s, #1
+** add z0\.s, z0\.s, z0\.s
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_s32_x_tied1, svint32_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_s32_x_tied1, svint32_t,
/*
** lsl_wide_1_s32_x_untied:
-** lsl z0\.s, z1\.s, #1
+** add z0\.s, z1\.s, z1\.s
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_s32_x_untied, svint32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c
index 5847db7bd97f..d14e314e9ded 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_s8_x_untied, svint8_t,
uint64_t,
/*
** lsl_wide_1_s8_x_tied1:
-** lsl z0\.b, z0\.b, #1
+** add z0\.b, z0\.b, z0\.b
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_s8_x_tied1, svint8_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_s8_x_tied1, svint8_t,
/*
** lsl_wide_1_s8_x_untied:
-** lsl z0\.b, z1\.b, #1
+** add z0\.b, z1\.b, z1\.b
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_s8_x_untied, svint8_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c
index 2c047b7f7e5c..154f7bd0bad9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_u16_x_untied, svuint16_t,
uint64_t,
/*
** lsl_wide_1_u16_x_tied1:
-** lsl z0\.h, z0\.h, #1
+** add z0\.h, z0\.h, z0\.h
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_u16_x_tied1, svuint16_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_u16_x_tied1, svuint16_t,
/*
** lsl_wide_1_u16_x_untied:
-** lsl z0\.h, z1\.h, #1
+** add z0\.h, z1\.h, z1\.h
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_u16_x_untied, svuint16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c
index 1e149633473b..d059d68e8323 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_u32_x_untied, svuint32_t,
uint64_t,
/*
** lsl_wide_1_u32_x_tied1:
-** lsl z0\.s, z0\.s, #1
+** add z0\.s, z0\.s, z0\.s
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_u32_x_tied1, svuint32_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_u32_x_tied1, svuint32_t,
/*
** lsl_wide_1_u32_x_untied:
-** lsl z0\.s, z1\.s, #1
+** add z0\.s, z1\.s, z1\.s
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_u32_x_untied, svuint32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c
index 55f272170779..503e101e5aa5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_u8_x_untied, svuint8_t,
uint64_t,
/*
** lsl_wide_1_u8_x_tied1:
-** lsl z0\.b, z0\.b, #1
+** add z0\.b, z0\.b, z0\.b
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_u8_x_tied1, svuint8_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_u8_x_tied1, svuint8_t,
/*
** lsl_wide_1_u8_x_untied:
-** lsl z0\.b, z1\.b, #1
+** add z0\.b, z1\.b, z1\.b
** ret
*/
TEST_UNIFORM_Z (lsl_wide_1_u8_x_untied, svuint8_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c
index ff477685a01c..9eaa0d177d0b 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c
@@ -29,12 +29,10 @@
TEST_ALL (LOOP)
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 4 } } */
/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.b,} } } */
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h,} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 4 } } */
/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.h,} } } */
/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.s,} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_6.c
b/gcc/testsuite/gcc.target/aarch64/sve/adr_6.c
index 1f927493a8fd..13e226433766 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/adr_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_6.c
@@ -31,8 +31,8 @@ TEST_TYPE (uint16_t, 128)
TEST_TYPE (int32_t, 128)
TEST_TYPE (uint32_t, 128)
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 6 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 6 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 8 } } */
+/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 4 } } */
/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s,
z[0-9]+\.s, lsl #?1\]\n} 4 } } */
/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s,
z[0-9]+\.s, lsl #?2\]\n} 4 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7.c
index 5561f4219790..e11a4554077e 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7.c
@@ -31,19 +31,19 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 2 }
} */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b, z[0-9]+\.b,
z[0-9]+\.b\n} 2 } } */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 2 }
} */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #7\n} 2 }
} */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 2 }
} */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h,
z[0-9]+\.h\n} 2 } } */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #2\n} 2 }
} */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #15\n} 2
} } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #1\n} 2 }
} */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s,
z[0-9]+\.s\n} 2 } } */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #2\n} 2 }
} */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #31\n} 2
} } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #1\n} 2 }
} */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d,
z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #2\n} 2 }
} */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #63\n} 2
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8.c
index d5549272e570..7db3f6233dac 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8.c
@@ -31,19 +31,19 @@
TEST_ALL (DEF_LOOP)
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 2 }
} */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b, z[0-9]+\.b,
z[0-9]+\.b\n} 2 } } */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 2 }
} */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #7\n} 2 }
} */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 2 }
} */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h,
z[0-9]+\.h\n} 2 } } */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #2\n} 2 }
} */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #15\n} 2
} } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #1\n} 2 }
} */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s,
z[0-9]+\.s\n} 2 } } */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #2\n} 2 }
} */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #31\n} 2
} } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #1\n} 2 }
} */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d,
z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #2\n} 2 }
} */
/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #63\n} 2
} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/shift_2.c
b/gcc/testsuite/gcc.target/aarch64/sve/shift_2.c
index b7462c47db93..c1eadf015f0c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/shift_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/shift_2.c
@@ -44,9 +44,9 @@ TEST_TYPE (uint32_t, 128, 31)
/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h,
z[0-9]+\.h\n} 2 } } */
/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s,
z[0-9]+\.s\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 6 }
} */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 4 }
} */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #1\n} 2 }
} */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b, z[0-9]+\.b,
z[0-9]+\.b\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h,
z[0-9]+\.h\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s,
z[0-9]+\.s\n} 2 } } */
/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 3 }
} */
/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 2 }
} */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/sve_shl_add.c
b/gcc/testsuite/gcc.target/aarch64/sve/sve_shl_add.c
new file mode 100644
index 000000000000..6b370af0aa5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/sve_shl_add.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O3" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+#define FUNC(NAME, OPERATION, IMMEDIATE) \
+void NAME(int n) { \
+ for (int i = 0; i < n; i++) \
+ out[i] = in[i] OPERATION IMMEDIATE; \
+} \
+
+#define N 1024
+
+int out[N], in[N];
+
+/*
+** foo:
+** ...
+** add z[0-9]+.s, z[0-9]+.s, z[0-9]+.s
+** ...
+*/
+FUNC(foo, <<, 1)
+
+/*
+** foo2:
+** ...
+** lsl z[0-9]+.s, z[0-9]+.s, #15
+** ...
+*/
+FUNC(foo2, <<, 15)
+
+/*
+** foo3:
+** ...
+** asr z[0-9]+.s, z[0-9]+.s, #1
+** ...
+*/
+FUNC(foo3, >>, 1)
+
+/*
+** foo4:
+** ...
+** asr z[0-9]+.s, z[0-9]+.s, #10
+** ...
+*/
+FUNC(foo4, >>, 10)
diff --git
a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_s64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_s64.c
index 4ea3335a29fa..4093990750dc 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_s64.c
@@ -204,7 +204,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_untied_s64_u64offset,
svint64_t, int16_t, sv
/*
** ldnt1sh_gather_x0_s64_s64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -214,7 +214,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_x0_s64_s64index,
svint64_t, int16_t, svint64
/*
** ldnt1sh_gather_tied1_s64_s64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -224,7 +224,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_tied1_s64_s64index,
svint64_t, int16_t, svin
/*
** ldnt1sh_gather_untied_s64_s64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -234,7 +234,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_untied_s64_s64index,
svint64_t, int16_t, svi
/*
** ldnt1sh_gather_x0_s64_u64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -244,7 +244,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_x0_s64_u64index,
svint64_t, int16_t, svuint6
/*
** ldnt1sh_gather_tied1_s64_u64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -254,7 +254,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_tied1_s64_u64index,
svint64_t, int16_t, svui
/*
** ldnt1sh_gather_untied_s64_u64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
diff --git
a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_u64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_u64.c
index 18c8ca44e7b8..afc920e57114 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_u64.c
@@ -204,7 +204,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_untied_u64_u64offset,
svuint64_t, int16_t, s
/*
** ldnt1sh_gather_x0_u64_s64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -214,7 +214,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_x0_u64_s64index,
svuint64_t, int16_t, svint6
/*
** ldnt1sh_gather_tied1_u64_s64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -224,7 +224,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_tied1_u64_s64index,
svuint64_t, int16_t, svi
/*
** ldnt1sh_gather_untied_u64_s64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -234,7 +234,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_untied_u64_s64index,
svuint64_t, int16_t, sv
/*
** ldnt1sh_gather_x0_u64_u64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -244,7 +244,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_x0_u64_u64index,
svuint64_t, int16_t, svuint
/*
** ldnt1sh_gather_tied1_u64_u64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -254,7 +254,7 @@ TEST_LOAD_GATHER_SZ (ldnt1sh_gather_tied1_u64_u64index,
svuint64_t, int16_t, svu
/*
** ldnt1sh_gather_untied_u64_u64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** ldnt1sh z0\.d, p0/z, \[\1, x0\]
** ret
*/
diff --git
a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_s64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_s64.c
index be2e6d126e80..a4685088b510 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_s64.c
@@ -204,7 +204,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_untied_s64_u64offset,
svint64_t, uint16_t, s
/*
** ldnt1uh_gather_x0_s64_s64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -214,7 +214,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_x0_s64_s64index,
svint64_t, uint16_t, svint6
/*
** ldnt1uh_gather_tied1_s64_s64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -224,7 +224,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_tied1_s64_s64index,
svint64_t, uint16_t, svi
/*
** ldnt1uh_gather_untied_s64_s64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -234,7 +234,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_untied_s64_s64index,
svint64_t, uint16_t, sv
/*
** ldnt1uh_gather_x0_s64_u64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -244,7 +244,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_x0_s64_u64index,
svint64_t, uint16_t, svuint
/*
** ldnt1uh_gather_tied1_s64_u64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -254,7 +254,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_tied1_s64_u64index,
svint64_t, uint16_t, svu
/*
** ldnt1uh_gather_untied_s64_u64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
diff --git
a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_u64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_u64.c
index e3bc1044cd7c..ffcbf1f4d8b4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_u64.c
@@ -204,7 +204,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_untied_u64_u64offset,
svuint64_t, uint16_t,
/*
** ldnt1uh_gather_x0_u64_s64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -214,7 +214,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_x0_u64_s64index,
svuint64_t, uint16_t, svint
/*
** ldnt1uh_gather_tied1_u64_s64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -224,7 +224,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_tied1_u64_s64index,
svuint64_t, uint16_t, sv
/*
** ldnt1uh_gather_untied_u64_s64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -234,7 +234,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_untied_u64_s64index,
svuint64_t, uint16_t, s
/*
** ldnt1uh_gather_x0_u64_u64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -244,7 +244,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_x0_u64_u64index,
svuint64_t, uint16_t, svuin
/*
** ldnt1uh_gather_tied1_u64_u64index:
-** lsl (z[0-9]+\.d), z0\.d, #1
+** add (z[0-9]+\.d), z0\.d, z0\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
@@ -254,7 +254,7 @@ TEST_LOAD_GATHER_SZ (ldnt1uh_gather_tied1_u64_u64index,
svuint64_t, uint16_t, sv
/*
** ldnt1uh_gather_untied_u64_u64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** ldnt1h z0\.d, p0/z, \[\1, x0\]
** ret
*/
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s16.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s16.c
index 103af35782c1..6bd88dca86cd 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s16.c
@@ -361,7 +361,7 @@ TEST_UNIFORM_Z (rshl_m1_s16_x_untied, svint16_t,
/*
** rshl_1_s16_x_tied1:
-** lsl z0\.h, z0\.h, #1
+** add z0\.h, z0\.h, z0\.h
** ret
*/
TEST_UNIFORM_Z (rshl_1_s16_x_tied1, svint16_t,
@@ -370,7 +370,7 @@ TEST_UNIFORM_Z (rshl_1_s16_x_tied1, svint16_t,
/*
** rshl_1_s16_x_untied:
-** lsl z0\.h, z1\.h, #1
+** add z0\.h, z1\.h, z1\.h
** ret
*/
TEST_UNIFORM_Z (rshl_1_s16_x_untied, svint16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s32.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s32.c
index 542c857c9e28..450a45ba2da4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s32.c
@@ -361,7 +361,7 @@ TEST_UNIFORM_Z (rshl_m1_s32_x_untied, svint32_t,
/*
** rshl_1_s32_x_tied1:
-** lsl z0\.s, z0\.s, #1
+** add z0\.s, z0\.s, z0\.s
** ret
*/
TEST_UNIFORM_Z (rshl_1_s32_x_tied1, svint32_t,
@@ -370,7 +370,7 @@ TEST_UNIFORM_Z (rshl_1_s32_x_tied1, svint32_t,
/*
** rshl_1_s32_x_untied:
-** lsl z0\.s, z1\.s, #1
+** add z0\.s, z1\.s, z1\.s
** ret
*/
TEST_UNIFORM_Z (rshl_1_s32_x_untied, svint32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s64.c
index b85fbb51a2c9..3e54707ba4ce 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s64.c
@@ -361,7 +361,7 @@ TEST_UNIFORM_Z (rshl_m1_s64_x_untied, svint64_t,
/*
** rshl_1_s64_x_tied1:
-** lsl z0\.d, z0\.d, #1
+** add z0\.d, z0\.d, z0\.d
** ret
*/
TEST_UNIFORM_Z (rshl_1_s64_x_tied1, svint64_t,
@@ -370,7 +370,7 @@ TEST_UNIFORM_Z (rshl_1_s64_x_tied1, svint64_t,
/*
** rshl_1_s64_x_untied:
-** lsl z0\.d, z1\.d, #1
+** add z0\.d, z1\.d, z1\.d
** ret
*/
TEST_UNIFORM_Z (rshl_1_s64_x_untied, svint64_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s8.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s8.c
index f33102ce6bd5..7ba2d7c68cfc 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_s8.c
@@ -361,7 +361,7 @@ TEST_UNIFORM_Z (rshl_m1_s8_x_untied, svint8_t,
/*
** rshl_1_s8_x_tied1:
-** lsl z0\.b, z0\.b, #1
+** add z0\.b, z0\.b, z0\.b
** ret
*/
TEST_UNIFORM_Z (rshl_1_s8_x_tied1, svint8_t,
@@ -370,7 +370,7 @@ TEST_UNIFORM_Z (rshl_1_s8_x_tied1, svint8_t,
/*
** rshl_1_s8_x_untied:
-** lsl z0\.b, z1\.b, #1
+** add z0\.b, z1\.b, z1\.b
** ret
*/
TEST_UNIFORM_Z (rshl_1_s8_x_untied, svint8_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u16.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u16.c
index 3b7abfe5400a..2b01b9fd586c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u16.c
@@ -361,7 +361,7 @@ TEST_UNIFORM_Z (rshl_m1_u16_x_untied, svuint16_t,
/*
** rshl_1_u16_x_tied1:
-** lsl z0\.h, z0\.h, #1
+** add z0\.h, z0\.h, z0\.h
** ret
*/
TEST_UNIFORM_Z (rshl_1_u16_x_tied1, svuint16_t,
@@ -370,7 +370,7 @@ TEST_UNIFORM_Z (rshl_1_u16_x_tied1, svuint16_t,
/*
** rshl_1_u16_x_untied:
-** lsl z0\.h, z1\.h, #1
+** add z0\.h, z1\.h, z1\.h
** ret
*/
TEST_UNIFORM_Z (rshl_1_u16_x_untied, svuint16_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u32.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u32.c
index ed86ae0c1672..c659987b2b7d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u32.c
@@ -361,7 +361,7 @@ TEST_UNIFORM_Z (rshl_m1_u32_x_untied, svuint32_t,
/*
** rshl_1_u32_x_tied1:
-** lsl z0\.s, z0\.s, #1
+** add z0\.s, z0\.s, z0\.s
** ret
*/
TEST_UNIFORM_Z (rshl_1_u32_x_tied1, svuint32_t,
@@ -370,7 +370,7 @@ TEST_UNIFORM_Z (rshl_1_u32_x_tied1, svuint32_t,
/*
** rshl_1_u32_x_untied:
-** lsl z0\.s, z1\.s, #1
+** add z0\.s, z1\.s, z1\.s
** ret
*/
TEST_UNIFORM_Z (rshl_1_u32_x_untied, svuint32_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u64.c
index cd92206a0d3d..23b493008749 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u64.c
@@ -361,7 +361,7 @@ TEST_UNIFORM_Z (rshl_m1_u64_x_untied, svuint64_t,
/*
** rshl_1_u64_x_tied1:
-** lsl z0\.d, z0\.d, #1
+** add z0\.d, z0\.d, z0\.d
** ret
*/
TEST_UNIFORM_Z (rshl_1_u64_x_tied1, svuint64_t,
@@ -370,7 +370,7 @@ TEST_UNIFORM_Z (rshl_1_u64_x_tied1, svuint64_t,
/*
** rshl_1_u64_x_untied:
-** lsl z0\.d, z1\.d, #1
+** add z0\.d, z1\.d, z1\.d
** ret
*/
TEST_UNIFORM_Z (rshl_1_u64_x_untied, svuint64_t,
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u8.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u8.c
index 4cc0036af5f5..39507b1bdc5f 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rshl_u8.c
@@ -361,7 +361,7 @@ TEST_UNIFORM_Z (rshl_m1_u8_x_untied, svuint8_t,
/*
** rshl_1_u8_x_tied1:
-** lsl z0\.b, z0\.b, #1
+** add z0\.b, z0\.b, z0\.b
** ret
*/
TEST_UNIFORM_Z (rshl_1_u8_x_tied1, svuint8_t,
@@ -370,7 +370,7 @@ TEST_UNIFORM_Z (rshl_1_u8_x_tied1, svuint8_t,
/*
** rshl_1_u8_x_untied:
-** lsl z0\.b, z1\.b, #1
+** add z0\.b, z1\.b, z1\.b
** ret
*/
TEST_UNIFORM_Z (rshl_1_u8_x_untied, svuint8_t,
diff --git
a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_s64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_s64.c
index 006e0e24dec1..07f9c08efea2 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_s64.c
@@ -177,7 +177,7 @@ TEST_STORE_SCATTER_SZ (stnt1h_scatter_s64_u64offset,
svint64_t, int16_t, svuint6
/*
** stnt1h_scatter_x0_s64_s64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** stnt1h z0\.d, p0, \[\1, x0\]
** ret
*/
@@ -187,7 +187,7 @@ TEST_STORE_SCATTER_SZ (stnt1h_scatter_x0_s64_s64index,
svint64_t, int16_t, svint
/*
** stnt1h_scatter_s64_s64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** stnt1h z0\.d, p0, \[\1, x0\]
** ret
*/
@@ -197,7 +197,7 @@ TEST_STORE_SCATTER_SZ (stnt1h_scatter_s64_s64index,
svint64_t, int16_t, svint64_
/*
** stnt1h_scatter_x0_s64_u64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** stnt1h z0\.d, p0, \[\1, x0\]
** ret
*/
@@ -207,7 +207,7 @@ TEST_STORE_SCATTER_SZ (stnt1h_scatter_x0_s64_u64index,
svint64_t, int16_t, svuin
/*
** stnt1h_scatter_s64_u64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** stnt1h z0\.d, p0, \[\1, x0\]
** ret
*/
diff --git
a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_u64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_u64.c
index 972ee36896b5..792e10c7ad18 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_u64.c
@@ -177,7 +177,7 @@ TEST_STORE_SCATTER_SZ (stnt1h_scatter_u64_u64offset,
svuint64_t, uint16_t, svuin
/*
** stnt1h_scatter_x0_u64_s64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** stnt1h z0\.d, p0, \[\1, x0\]
** ret
*/
@@ -187,7 +187,7 @@ TEST_STORE_SCATTER_SZ (stnt1h_scatter_x0_u64_s64index,
svuint64_t, uint16_t, svi
/*
** stnt1h_scatter_u64_s64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** stnt1h z0\.d, p0, \[\1, x0\]
** ret
*/
@@ -197,7 +197,7 @@ TEST_STORE_SCATTER_SZ (stnt1h_scatter_u64_s64index,
svuint64_t, uint16_t, svint6
/*
** stnt1h_scatter_x0_u64_u64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** stnt1h z0\.d, p0, \[\1, x0\]
** ret
*/
@@ -207,7 +207,7 @@ TEST_STORE_SCATTER_SZ (stnt1h_scatter_x0_u64_u64index,
svuint64_t, uint16_t, svu
/*
** stnt1h_scatter_u64_u64index:
-** lsl (z[0-9]+\.d), z1\.d, #1
+** add (z[0-9]+\.d), z1\.d, z1\.d
** stnt1h z0\.d, p0, \[\1, x0\]
** ret
*/
