https://gcc.gnu.org/g:0a16b1b97c112e41a0d37235e83678a67abd9454
commit r13-9011-g0a16b1b97c112e41a0d37235e83678a67abd9454
Author: Haochen Jiang <haochen.ji...@intel.com>
Date: Fri Sep 6 11:19:26 2024 +0800
doc: Enhance Intel CPU documentation
This patch will add those recent aliased CPU names into documentation
for clearness, partly backported from GCC15 trunk patch.
gcc/ChangeLog:
PR target/116617
* doc/invoke.texi: Add meteorlake, raptorlake and lunarlake.
Diff:
---
gcc/doc/invoke.texi | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b17d0cf93411..0f665ed6779a 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -32532,12 +32532,14 @@ UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI,
AVX512-FP16 and AVX512BF16
instruction set support.
@item alderlake
-Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES,
-XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B,
-CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU,
-VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL and AVX-VNNI instruction set
-support.
+@itemx raptorlake
+@itemx meteorlake
+Intel Alderlake/Raptorlake/Meteorlake CPU with 64-bit extensions, MOVBE, MMX,
+SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND,
+XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB,
+MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA,
+LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL and
+AVX-VNNI instruction set support.
@item rocketlake
Intel Rocketlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3
