https://gcc.gnu.org/g:6749c69ae143ed808e0d0aa9097f0c9b7c6a785d
commit r15-3528-g6749c69ae143ed808e0d0aa9097f0c9b7c6a785d
Author: Zhao Dingyi <dingyizhao....@outlook.com>
Date: Sat Sep 7 10:48:46 2024 -0600
[PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model
This patch aims to add the missing instruction types to the XiangShan-Nanhu
scheduler model.
The current XiangShan -Nanhu model lacks the trap, atomic trap, fcvt_i2f,
and fcvt_f2i instructions.
The trap, atomic, and i2f instructions belong to xs_jmp_rs. [1]
The f2i instruction belongs to xs_fmisc_rs.[2]
[1]
https://github.com/OpenXiangShan/XiangShan/blob/v2.0/src/main/scala/xiangshan/package.scala#L780
[2]
https://github.com/OpenXiangShan/XiangShan/blob/v2.0/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala#L290
gcc/ChangeLog:
* config/riscv/xiangshan.md: Add atomic, trap, fcvt_i2f, fcvt_f2i.
Diff:
---
gcc/config/riscv/xiangshan.md | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md
index 76539d332b82..eb83bbff1beb 100644
--- a/gcc/config/riscv/xiangshan.md
+++ b/gcc/config/riscv/xiangshan.md
@@ -70,12 +70,17 @@
(define_insn_reservation "xiangshan_jump" 1
(and (eq_attr "tune" "xiangshan")
- (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu"))
+ (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu,trap"))
"xs_jmp_rs")
(define_insn_reservation "xiangshan_i2f" 3
(and (eq_attr "tune" "xiangshan")
- (eq_attr "type" "mtc"))
+ (eq_attr "type" "mtc,fcvt_i2f"))
+ "xs_jmp_rs")
+
+(define_insn_reservation "xiangshan_atomic" 1
+ (and (eq_attr "tune" "xiangshan")
+ (eq_attr "type" "atomic"))
"xs_jmp_rs")
(define_insn_reservation "xiangshan_mul" 3
@@ -115,7 +120,7 @@
(define_insn_reservation "xiangshan_f2f" 3
(and (eq_attr "tune" "xiangshan")
- (eq_attr "type" "fcvt,fmove"))
+ (eq_attr "type" "fcvt,fcvt_f2i,fmove"))
"xs_fmisc_rs")
(define_insn_reservation "xiangshan_f2i" 3
