https://gcc.gnu.org/g:51aee40c9d5d97b45d7d96781e1f43c9100702f6
commit 51aee40c9d5d97b45d7d96781e1f43c9100702f6
Author: Pan Li <pan2...@intel.com>
Date: Tue Aug 27 15:14:40 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4
This patch would like to add test cases for the unsigned scalar
.SAT_SUB IMM form 4. Aka:
Form 4:
#define DEF_SAT_U_SUB_IMM_FMT_4(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_4 (T x) \
{ \
return x > (T)IMM ? x - (T)IMM : 0; \
}
DEF_SAT_U_SUB_IMM_FMT_4(uint64_t, 23)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_sub_imm-13.c: New test.
* gcc.target/riscv/sat_u_sub_imm-13_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-13_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-14.c: New test.
* gcc.target/riscv/sat_u_sub_imm-14_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-14_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-15.c: New test.
* gcc.target/riscv/sat_u_sub_imm-15_1.c: New test.
* gcc.target/riscv/sat_u_sub_imm-15_2.c: New test.
* gcc.target/riscv/sat_u_sub_imm-16.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-13.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-14.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-15.c: New test.
* gcc.target/riscv/sat_u_sub_imm-run-16.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
(cherry picked from commit 3989e31d867b3505f847ecb6d870eacacfdf47bf)
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 9 ++++
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13.c | 19 ++++++++
.../gcc.target/riscv/sat_u_sub_imm-13_1.c | 19 ++++++++
.../gcc.target/riscv/sat_u_sub_imm-13_2.c | 19 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14.c | 20 ++++++++
.../gcc.target/riscv/sat_u_sub_imm-14_1.c | 21 +++++++++
.../gcc.target/riscv/sat_u_sub_imm-14_2.c | 22 +++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15.c | 19 ++++++++
.../gcc.target/riscv/sat_u_sub_imm-15_1.c | 21 +++++++++
.../gcc.target/riscv/sat_u_sub_imm-15_2.c | 22 +++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-16.c | 18 +++++++
.../gcc.target/riscv/sat_u_sub_imm-run-13.c | 55 ++++++++++++++++++++++
.../gcc.target/riscv/sat_u_sub_imm-run-14.c | 55 ++++++++++++++++++++++
.../gcc.target/riscv/sat_u_sub_imm-run-15.c | 54 +++++++++++++++++++++
.../gcc.target/riscv/sat_u_sub_imm-run-16.c | 48 +++++++++++++++++++
15 files changed, 421 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 406ac1d65db..4e91821a1c8 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -222,6 +222,13 @@ sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \
return (T)IMM > y ? (T)IMM - y : 0; \
}
+#define DEF_SAT_U_SUB_IMM_FMT_4(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_sub_imm##IMM##_##T##_fmt_4 (T x) \
+{ \
+ return x > (T)IMM ? x - (T)IMM : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -241,6 +248,8 @@ sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \
if (sat_u_sub_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
#define RUN_SAT_U_SUB_IMM_FMT_3(T, IMM, y, expect) \
if (sat_u_sub_imm##IMM##_##T##_fmt_3(y) != expect) __builtin_abort ()
+#define RUN_SAT_U_SUB_IMM_FMT_4(T, x, IMM, expect) \
+ if (sat_u_sub_imm##IMM##_##T##_fmt_4(x) != expect) __builtin_abort ()
/******************************************************************************/
/* Saturation Truncate (unsigned and signed)
*/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13.c
new file mode 100644
index 00000000000..7dcbc3b1a12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm11_uint8_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*-11
+** sltiu\s+a0,\s*[atx][0-9]+,\s*11
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 11)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13_1.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13_1.c
new file mode 100644
index 00000000000..ec902880e82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13_1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm128_uint8_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*-128
+** sltiu\s+a0,\s*[atx][0-9]+,\s*128
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 128)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13_2.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13_2.c
new file mode 100644
index 00000000000..4fa33a702c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-13_2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm253_uint8_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*-253
+** sltiu\s+a0,\s*[atx][0-9]+,\s*253
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 253)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14.c
new file mode 100644
index 00000000000..45db6339b78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm6_uint16_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*-6
+** sltiu\s+a0,\s*[atx][0-9]+,\s*6
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 6)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14_1.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14_1.c
new file mode 100644
index 00000000000..d8a35fe2dec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14_1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm32768_uint16_t_fmt_4:
+** li\s+[atx][0-9]+,\s*32768
+** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 32768)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14_2.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14_2.c
new file mode 100644
index 00000000000..35509f22f30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-14_2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm65533_uint16_t_fmt_4:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3
+** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 65533)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15.c
new file mode 100644
index 00000000000..7614dc885fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm255_uint32_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*-255
+** sltiu\s+a0,\s*[atx][0-9]+,\s*255
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint32_t, 255)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15_1.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15_1.c
new file mode 100644
index 00000000000..c6b8e5ba3d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15_1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm2147483648_uint32_t_fmt_2:
+** li\s+[atx][0-9]+,\s*1
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31
+** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483648)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15_2.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15_2.c
new file mode 100644
index 00000000000..d3f94a10cf9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15_2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm68719476732_uint32_t_fmt_2:
+** li\s+[atx][0-9]+,\s*1
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4
+** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 68719476732)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-16.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-16.c
new file mode 100644
index 00000000000..898349d4f66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-16.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm82_uint64_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-82
+** sltiu\s+a0,\s*[atx][0-9]+,\s*82
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 82)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-13.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-13.c
new file mode 100644
index 00000000000..603f2eeab84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-13.c
@@ -0,0 +1,55 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 2)
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 6)
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 129)
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 254)
+DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_SUB_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 1, 0, 1, },
+ { 1, 255, 0, },
+ { 254, 254, 0, },
+ { 254, 255, 0, },
+ { 254, 2, 252, },
+ { 255, 254, 1, },
+ { 255, 0, 255, },
+ { 5, 2, 3, },
+ { 5, 6, 0, },
+ { 127, 0, 127, },
+ { 128, 129, 0, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 0, d[1][2]);
+ RUN (T, d[2][0], 255, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 255, d[4][2]);
+ RUN (T, d[5][0], 2, d[5][2]);
+
+ RUN (T, d[6][0], 254, d[6][2]);
+ RUN (T, d[7][0], 0, d[7][2]);
+
+ RUN (T, d[8][0], 2, d[8][2]);
+ RUN (T, d[9][0], 6, d[9][2]);
+
+ RUN (T, d[10][0], 0, d[10][2]);
+
+ RUN (T, d[11][0], 129, d[11][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-14.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-14.c
new file mode 100644
index 00000000000..610e02124cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-14.c
@@ -0,0 +1,55 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 2)
+DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 6)
+DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 32767)
+DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 65534)
+DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_SUB_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 1, 0, 1, },
+ { 1, 65535, 0, },
+ { 65534, 65534, 0, },
+ { 65534, 65535, 0, },
+ { 65534, 2, 65532, },
+ { 65535, 65534, 1, },
+ { 65535, 0, 65535, },
+ { 5, 2, 3, },
+ { 5, 6, 0, },
+ { 32767, 0, 32767, },
+ { 32768, 32767, 1, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 0, d[1][2]);
+ RUN (T, d[2][0], 65535, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65535, d[4][2]);
+ RUN (T, d[5][0], 2, d[5][2]);
+
+ RUN (T, d[6][0], 65534, d[6][2]);
+ RUN (T, d[7][0], 0, d[7][2]);
+
+ RUN (T, d[8][0], 2, d[8][2]);
+ RUN (T, d[9][0], 6, d[9][2]);
+
+ RUN (T, d[10][0], 0, d[10][2]);
+
+ RUN (T, d[11][0], 32767, d[11][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-15.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-15.c
new file mode 100644
index 00000000000..1d9e0cbbbfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-15.c
@@ -0,0 +1,54 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint32_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_4(uint32_t, 2)
+DEF_SAT_U_SUB_IMM_FMT_4(uint32_t, 6)
+DEF_SAT_U_SUB_IMM_FMT_4(uint32_t, 2147483647)
+DEF_SAT_U_SUB_IMM_FMT_4(uint32_t, 4294967294)
+DEF_SAT_U_SUB_IMM_FMT_4(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_SUB_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 1, 0, 1, },
+ { 1, 4294967295, 0, },
+ { 4294967294, 4294967294, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967294, 2, 4294967292, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 0, 4294967295, },
+ { 5, 2, 3, },
+ { 5, 6, 0, },
+ { 2147483647, 0, 2147483647, },
+ { 2147483648, 2147483647, 1, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 0, d[1][2]);
+ RUN (T, d[2][0], 4294967295, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967295, d[4][2]);
+ RUN (T, d[5][0], 2, d[5][2]);
+
+ RUN (T, d[6][0], 4294967294, d[6][2]);
+ RUN (T, d[7][0], 0, d[7][2]);
+
+ RUN (T, d[8][0], 2, d[8][2]);
+ RUN (T, d[9][0], 6, d[9][2]);
+
+ RUN (T, d[10][0], 0, d[10][2]);
+ RUN (T, d[11][0], 2147483647, d[11][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-16.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-16.c
new file mode 100644
index 00000000000..f864a67220c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-16.c
@@ -0,0 +1,48 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_4(uint64_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_4(uint64_t, 2)
+DEF_SAT_U_SUB_IMM_FMT_4(uint64_t, 6)
+DEF_SAT_U_SUB_IMM_FMT_4(uint64_t, 18446744073709551614u)
+DEF_SAT_U_SUB_IMM_FMT_4(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, imm, op, expect) RUN_SAT_U_SUB_IMM_FMT_4(T, imm, op, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 1, 0, 1, },
+ { 1, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551614u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 2, 18446744073709551612u, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 0, 18446744073709551615u, },
+ { 5, 2, 3, },
+ { 5, 6, 0, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 0, d[1][2]);
+ RUN (T, d[2][0], 18446744073709551615u, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551615u, d[4][2]);
+ RUN (T, d[5][0], 2, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551614u, d[6][2]);
+ RUN (T, d[7][0], 0, d[7][2]);
+
+ RUN (T, d[8][0], 2, d[8][2]);
+ RUN (T, d[9][0], 6, d[9][2]);
+
+ return 0;
+}
