https://gcc.gnu.org/g:ac5d971847f7f63d01640c79d63cd783b97d1073
commit ac5d971847f7f63d01640c79d63cd783b97d1073 Author: Xiao Zeng <[email protected]> Date: Mon May 6 15:57:37 2024 -0600 [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option This patch would like to add new sub extension (aka Zfbfmin) to the -march= option. It introduces a new data type BF16. 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S. 3 Zfhmin extension depend on 'F'. 4 Simply put, just make Zfbfmin dependent on Zfhmin. Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and FMV.H.X instructions an independent extension to achieve precise dependency relationships for the Zfbfmin. You can locate more information about Zfbfmin from below spec doc. <https://github.com/riscv/riscv-bfloat16/releases/download/v59042fc71c31a9bcb2f1957621c960ed36fac401/riscv-bfloat16.pdf> gcc/ * common/config/riscv/riscv-common.cc (riscv_implied_info): zfbfmin implies zfhmin. (riscv_ext_version_table, riscv_ext_flag_table): Add zfbfmin. * config/riscv/riscv.opt (ZFBFMIN): Add optoion. gcc/testsuite/ * gcc.target/riscv/arch-35.c: New test. * gcc.target/riscv/arch-36.c: New test. * gcc.target/riscv/predef-34.c: New test. * gcc.target/riscv/predef-35.c: New test. (cherry picked from commit 35224ead63732a3550ba4b1332c06e9dc7999c31) Diff: --- gcc/common/config/riscv/riscv-common.cc | 3 ++ gcc/config/riscv/riscv.opt | 2 ++ gcc/testsuite/gcc.target/riscv/arch-35.c | 5 ++++ gcc/testsuite/gcc.target/riscv/arch-36.c | 5 ++++ gcc/testsuite/gcc.target/riscv/predef-34.c | 47 ++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-35.c | 47 ++++++++++++++++++++++++++++++ 6 files changed, 109 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 1c71ea43f1d..3e52b7517ba 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -155,6 +155,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zvksed", "zve32x"}, {"zvksh", "zve32x"}, + {"zfbfmin", "zfhmin"}, {"zfh", "zfhmin"}, {"zfhmin", "f"}, @@ -331,6 +332,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1614,6 +1616,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, + {"zfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZFBFMIN}, {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, {"zvfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN}, diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 085dd616b63..9df0c26a561 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -393,6 +393,8 @@ Mask(ZIC64B) Var(riscv_zicmo_subext) TargetVariable int riscv_zf_subext +Mask(ZFBFMIN) Var(riscv_zf_subext) + Mask(ZFHMIN) Var(riscv_zf_subext) Mask(ZFH) Var(riscv_zf_subext) diff --git a/gcc/testsuite/gcc.target/riscv/arch-35.c b/gcc/testsuite/gcc.target/riscv/arch-35.c new file mode 100644 index 00000000000..6c783769666 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-35.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zfbfmin -mabi=ilp32f" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-36.c b/gcc/testsuite/gcc.target/riscv/arch-36.c new file mode 100644 index 00000000000..cbdccf12807 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-36.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_zfbfmin -mabi=lp64f" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-34.c b/gcc/testsuite/gcc.target/riscv/predef-34.c new file mode 100644 index 00000000000..0a993271f7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-34.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32i_zfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 32 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_zfhmin) +#error "__riscv_zfhmin" +#endif + +#if !defined(__riscv_zfbfmin) +#error "__riscv_zfbfmin" +#endif + +#if defined(__riscv_v) +#error "__riscv_v" +#endif + +#if defined(__riscv_d) +#error "__riscv_d" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-35.c b/gcc/testsuite/gcc.target/riscv/predef-35.c new file mode 100644 index 00000000000..76b328a8932 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-35.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64i_zfbfmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_zfhmin) +#error "__riscv_zfhmin" +#endif + +#if !defined(__riscv_zfbfmin) +#error "__riscv_zfbfmin" +#endif + +#if defined(__riscv_v) +#error "__riscv_v" +#endif + +#if defined(__riscv_d) +#error "__riscv_d" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + + return 0; +}
