The branch 'riscv/heads/gcc-14-with-riscv-opts' was updated to point to:
0a279dfd56e... Drop accidental hunk.
It previously pointed to:
99d15ac2752... [5/n][PR rtl-optimization/115877] Fix handling of input/out
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
-------------------------------------------------------------------
99d15ac... [5/n][PR rtl-optimization/115877] Fix handling of input/out
0ee41b0... RISC-V: Implement the .SAT_TRUNC for scalar
d4f5e86... [4/n][PR rtl-optimization/115877] Correct SUBREG handling i
316f961... [NFC][PR rtl-optimization/115877] Avoid setting irrelevant
97d9050... RISC-V: Rearrange the test helper files for vector .SAT_*
faadb6b... [PR rtl-optimization/115877][2/n] Improve liveness computat
3e82d57... [PR rtl-optimization/115877] Fix livein computation for ext
bdb2115... RISC-V: Fix testcase missing arch attribute
b33c9ee... Add debug counter for ext_dce
fa543ce... Fix liveness computation for shift/rotate counts in ext-dce
20fe3e2... Revert "RISC-V: Attribute parser: Use alloca() instead of n
4157d59... RISC-V: Allow adding enabled extension via target arch attr
fa716b3... RISC-V: Rewrite target attribute handling
64b4b52... RISC-V: Attribute parser: Use alloca() instead of new + std
2181463... RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark
e8be9b1... RISC-V: Implement locality for __builtin_prefetch
c2b212f... RISC-V: Add md files for vector BFloat16
958e43c... RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
a5ca595... RISC-V: Add vector type of BFloat16 format
ead3454... [PR rtl-optimization/115876] Fix one of two ubsan reported
67116d5... [RISC-V] Avoid unnecessary sign extension after memcmp
6322f7a... RISC-V: NO_WARNING preferred else value for RVV
d39d88e... RISC-V: Disable misaligned vector access in hook riscv_slow
68a2ba4... RISC-V: Add SiFive extensions, xsfvcp and xsfcease
e0bf7a4... [to-be-committed,RISC-V] Eliminate unnecessary sign extensi
1726acd... RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
b358677... RISC-V: c implies zca, and conditionally zcf & zcd
6b32e85... RISC-V: Update testsuite to use b
ac013ac... RISC-V: Add support for B standard extension
4649bea... RISC-V: fix zcmp popretz [PR113715]
16d1d5b... RISC-V: Fix comment/naming in attribute parsing code
6b9226f... RISC-V: Deduplicate arch subset list processing
6f19549... RISC-V: testsuite: Properly gate LTO tests
f3efae4... RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form
79aca63... RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form
d678469... [to-be-committed][RISC-V][V3] DCE analysis for extension el
cbee085... RISC-V: Implement .SAT_TRUNC for vector unsigned int
fe7b825... [RISC-V] add implied extension repeatly until stable
576d8c0... [to-be-committed][v3][RISC-V] Handle bit manipulation of SI
a3d53fe... RISC-V: fix internal error on global variable-length array
30267a9... RISC-V: Use tu policy for first-element vec_set [PR115725].
a2b380b... [committed][RISC-V] Fix test expectations after recent late
316bda6... RISC-V: Describe -march behavior for dependent extensions
de6abc8... RISC-V: Add support for Zabha extension
7013a45... RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR1157
b810058... RISC-V: Fix asm check failure for truncated after SAT_SUB
f97a257... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form
1ee1cae... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form
0d154f4... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form
170e8b6... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form
5bcf397... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi
86b900f... RISC-V: Add testcases for vector truncate after .SAT_SUB
09b41e9... RISC-V: Update testcase comments to point to PSABI rather t
001dc95... RISC-V: Consolidate amo testcase variants
0fe0038... RISC-V: Rename amo testcases
6925177... [committed][RISC-V] Fix expected output for thead store pai
6a975b9... [PATCH v2 3/3] RISC-V: cmpmem for RISCV with V extension
6113813... ira: Scale save/restore costs of callee save registers with
d46ded6... [committed][RISC-V] Fix some of the testsuite fallout from
46289ca... [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension
bf3011d... RISC-V: Add dg-remove-option for z* extensions
f3fecf5... [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_
378ceca... [committed][RISC-V][PR target/114139] Verify we have a CONS
43fd678... [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests
6d2cbb4... [PATCH v2] RISC-V: Remove integer vector eqne pattern
83ba88a... [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well
23e7e8c... [RISC-V] Minor cleanup/improvement to bset/binv patterns
eeead7e... [PATCH v2] RISC-V: Remove float vector eqne pattern
3eb4898... RISC-V: Promote Zaamo/Zalrsc to a when using an old binutil
19bab66... RISC-V: Add testcases for unsigned .SAT_SUB vector form 10
aea32d1... RISC-V: Add testcases for unsigned .SAT_SUB vector form 9
c353bc5... RISC-V: Add testcases for unsigned .SAT_SUB vector form 8
52b0df3... RISC-V: Add testcases for unsigned .SAT_SUB vector form 7
8106040... RISC-V: Add testcases for unsigned .SAT_SUB vector form 6
7ec128f... RISC-V: Add testcases for unsigned .SAT_SUB vector form 5
f48f96b... RISC-V: Add testcases for unsigned .SAT_SUB vector form 4
bee6a1a... RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
3d48857... RISC-V: Add testcases for unsigned .SAT_ADD vector form 8
ae1d941... RISC-V: Add testcases for unsigned .SAT_ADD vector form 7
d3690c6... RISC-V: Add testcases for unsigned .SAT_ADD vector form 6
684d632... RISC-V: Add testcases for unsigned .SAT_ADD vector form 5
6eae8ad... RISC-V: Add testcases for unsigned .SAT_ADD vector form 4
120e57e... RISC-V: Add testcases for unsigned .SAT_ADD vector form 3
ae07eb2... RISC-V: Add testcases for unsigned .SAT_ADD vector form 2
13eae3e... RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12
0fe89b6... RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11
47b3c4c... RISC-V: Move mode assertion out of conditional branch in em
23840c3... RISC-V: Fix vwsll combine on rv32 targets
835bf80... [committed] [RISC-V] Fix wrong patch application
5a8ee7d... [to-be-committed,RISC-V] Improve bset generation when bit p
bd78d15... [to-be-committed,RISC-V] Handle zero_extract destination fo
6af1fde... RISC-V: Add configure check for Zaamo/Zalrsc assembler supp
e0b2a59... [to-be-committed,RISC-V] Improve variable bit set for rv64
13a6b20... [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64
f8ebe03... RISC-V: Add testcases for vector unsigned SAT_SUB form 2
29b591a... riscv: Allocate enough space to strcpy() string
252ef61... RISC-V: Refine the SAT_ARITH test help header files [NFC]
ef69f0b... RISC-V: Add testcases for scalar unsigned SAT_SUB form 10
6354e41... RISC-V: Add testcases for scalar unsigned SAT_SUB form 9
50afa42... RISC-V: Add testcases for scalar unsigned SAT_SUB form 8
daeb325... RISC-V: Add testcases for scalar unsigned SAT_SUB form 7
6c3406f... RISC-V: Add testcases for scalar unsigned SAT_SUB form 6
094e1b8... RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
ea6644d... RISC-V: Add testcases for scalar unsigned SAT_SUB form 4
c633934... RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
1aa0928... RISC-V: Bugfix vec_extract v mode iterator restriction mism
04989c6... RISC-V: Add support for subword atomic loads/stores
e80e1db... RISC-V: Bugfix vec_extract vls mode iterator restriction mi
a457cce... Test: Move target independent test cases to gcc.dg/torture
92e2246... RISC-V: Allow any temp register to be used in amo tests
759a34e... RISC-V: Fix amoadd call arguments
9f9724b... RISC-V: Move amo tests into subfolder
a120ea6... RISC-V: Add Zalrsc amo-op patterns
b113651... RISC-V: Add Zalrsc and Zaamo testsuite support
73cd440... RISC-V: Add basic Zaamo and Zalrsc support
de50942... RISC-V: Implement .SAT_SUB for unsigned vector int
95948af... [committed] [RISC-V] Drop dead round_32 test
08a6582... [to-be-committed] [RISC-V] Use bext for extracting a bit in
1d97b9d... Just the testsuite bits from:
c5c054c... [to-be-committed] [RISC-V] Use bext for extracting a bit in
7cf4c1e... FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14
e0a5507... [committed] [RISC-V] Fix false-positive uninitialized varia
21b9c16... [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of
d63ee88... RISC-V: Implement .SAT_SUB for unsigned scalar int
1a6d2ed... RISC-V: Add testcases for scalar unsigned SAT_ADD form 5
b93df02... RISC-V: Add testcases for scalar unsigned SAT_ADD form 4
4b3c0b3... RISC-V: Add testcases for scalar unsigned SAT_ADD form 3
6f5119e... RISC-V: Add testcases for scalar unsigned SAT_ADD form 2
efe0057... RISC-V: Add testcases for scalar unsigned SAT_ADD form 1
4f20fec... RISC-V: Regenerate opt urls.
e46fc82... Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) fo
0e0b666... RISC-V: Introduce -mvector-strict-align.
f11cbf2... RISC-V: Add Zfbfmin extension
6eb2b85... tree-ssa-pre.c/115214(ICE in find_or_generate_expression, a
d9181d7... Just the riscv bits from:
e26b141... [to-be-committed] [RISC-V] Use Zbkb for general 64 bit cons
43c16b2... RISC-V: Remove dead perm series code and document.
36260f7... RISC-V: Add vector popcount, clz, ctz.
2ec5e6c... RISC-V: Add vandn combine helper.
5eade13... RISC-V: Use widening shift for scatter/gather if applicable
9d209e5... RISC-V: Add vwsll combine helpers.
a0fef33... RISC-V: Split vwadd.wx and vwsub.wx and add helpers.
901c9e9... RISC-V: Do not allow v0 as dest when merging [PR115068].
1ca0381... [to-be-committed] [RISC-V] Use pack to handle repeating con
95439d0... [to-be-committed] [RISC-V] Some basic patterns for zbkb cod
39e977a... RISC-V: Fix missing boolean_expression in zmmul extension
65e6ccc... [to-be-committed][RISC-V] Reassociate constants in logical
7f716ba... [to-be-committed] [RISC-V] Try inverting for constant synth
dbd78bc... [to-be-committed][RISC-V] Generate nearby constant, then ad
91f41ea... [committed] [v2] More logical op simplifications in simplif
b6c9219... [to-be-committed,v2,RISC-V] Use bclri in constant synthesis
cd9b981... RISC-V: Enable vectorization for vect-early-break_124-pr114
d85def2... RISC-V: avoid LUI based const mat in alloca epilogue expans
5f7595e... RISC-V: avoid LUI based const mat in prologue/epilogue expa
e42956a... Regenerate riscv.opt.urls and i386.opt.urls
98a4890... DSE: Fix ICE after allow vector type in get_stored_val
58349b4... [to-be-committed][RISC-V][PR target/115142] Do not create i
48ab926... RISC-V: Implement -m{,no}fence-tso
e043aa6... [to-be-committed,RISC-V] Improve some shift-add sequences
5b632ee... RISC-V: Fix "Nan-box the result of movbf on soft-bf16"
a320bcf... RISC-V: Modify _Bfloat16 to __bf16
0b3502c... RISC-V: Implement IFN SAT_ADD for both the scalar and vecto
7a46f67... RISC-V: Add initial cost handling for segment loads/stores.
12ceb8d... internal-fn: Do not force vcond_mask operands to reg.
9beeeba... RISC-V: Cleanup some temporally files [NFC]
2d6625b... RISC-V: Enable vectorizable early exit testsuite
a65f9b1... RISC-V: Implement vectorizable early exit with vcond_mask_l
f3aa413... Vect: Support loop len in vectorizable early exit
210fa5e... Vect: Support new IFN SAT_ADD for unsigned vector int
592205a... Internal-fn: Support new IFN SAT_ADD for unsigned scalar in
423d10a... RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi t
5b202f0... RISC-V: Add Zvfbfwma extension to the -march= option
d04ee59... Add missing hunk in recent change.
3411fe0... [v2,2/2] RISC-V: strcmp expansion: Use adjust_address() for
1687d67... [v2,1/2] RISC-V: Add cmpmemsi expansion
d8f7ba2... RISC-V: Test cbo.zero expansion for rv32
db2ad3d... RISC-V: Allow by-pieces to do overlapping accesses in block
15af00b... RISC-V: add tests for overlapping mem ops
242ebff... RISC-V: Allow unaligned accesses in cpymemsi expansion
3993646... RISC-V: Add test cases for cpymem expansion
184fca9... [committed] Fix rv32 issues with recent zicboz work
1db555a... [to-be-committed,RISC-V] Remove redundant AND in shift-add
b80fa21... RISC-V: avoid LUI based const materialization ... [part of
80bf573... [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero
547adc9... [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe
94b1fb8... [1/3] expr: Export clear_by_pieces()
4bcc64e... RISC-V: Fix format issue for trailing operator [NFC]
2d30998... [to-be-committed,RISC-V] Improve AND with some constants
7bee3e5... RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar
ab251bd... [to-be-committed,RISC-V] Improve single inverted bit extrac
a971125... [to-be-committed,RISC-V] Improve usage of slli.uw in consta
4853beb... [to-be-committed] RISC-V Fix minor regression in synthesis
972cb5c... [RISC-V] Use shNadd for constant synthesis
73fe7fd... RISC-V: Fix typos in code or comment [NFC]
a4b72b2... [committed] [RISC-V] Provide splitting guidance to combine
227ec9b... RISC-V: Make full-vec-move1.c test robust for optimization
9491284... RISC-V: Add tests for cpymemsi expansion
6c5e217... [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-
b30496a... [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usag
d3660f7... RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_exten
76f36d9... RISC-V: Add zero_extract support for rv64gc
31ab400... RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2
929ef4d... RISC-V: Add test for sraiw-31 special case
30096ff... [committed][RISC-V] Turn on overlap_op_by_pieces for generi
aeadd95... [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_
411f7cc... [RISC-V] [PATCH v2] Enable inlining str* by default
a38ee93... [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= op
03d11c2... RISC-V: Add testcase for PR114749.
1c61e73... [RISC-V] Add support for _Bfloat16
fdaac11... RISC-V: Document -mcmodel=large
6c0a8df... So another constant synthesis improvement.
4751ac4... RISC-V: miscll comment fixes [NFC]
733526b... [committed][RISC-V] Fix nearbyint failure on rv32 and forma
4313008... [RFA][RISC-V] Improve constant synthesis for constants with
d3c8cb9... [committed] [RISC-V] Don't run new rounding tests on newlib
1659526... [committed] [RISC-V] Trivial pattern cleanup
241fbf9... [committed] [RISC-V] Fix detection of store pair fusion cas
1f741dd... This is almost exclusively Jivan's work. His original post
0285854... RISC-V: Refine the condition for add additional vars in RVV
fe3b44c... RISC-V: Fix parsing of Zic* extensions
0761c4e... RISC-V: Add -X to link spec
Summary of changes (added commits):
-----------------------------------
0a279df... Drop accidental hunk.
e6b322c... Manual applicatoin of riscv specific changes from:
0c66fc4... Manual application of riscv specific changes from:
d9c50df... testsuite: fix dg-add-options vs. dg-options ordering
aa312da... Restrict pr116202-run-1.c test to riscv_v target
48816ef... RISC-V: Fix missing abi arg in test
8468423... Partial: Just the testsuite bits...
7192fa6... RISC-V: use fclass insns to implement isfinite,isnormal and
5433bd7... genoutput: Accelerate the place_operands function.
983da7a... RISC-V: Fix non-obvious comment typos
d0d826c... [RISC-V][PR target/116283] Fix split code for recent Zbs im
8eced56... RISC-V: Enable stack clash in alloca
9673f13... RISC-V: Add support to vector stack-clash protection
7f6b6a5... RISC-V: Stack-clash protection implemention
fec211c... RISC-V: Move riscv_v_adjust_scalable_frame
49000f5... RISC-V: Small stack tie changes
a9e84ce... RISC-V: rv32/DF: Prevent 2 SImode loads using XTheadMemIdx
c2fbe69... RISC-V: xthead(f)memidx: Eliminate optimization patterns
fef1236... RISC-V: testsuite: xtheadfmemidx: Rename test and add simil
05611fb... RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB'
616f63e... [RISC-V][PR target/116240] Ensure object is a comparison be
184712c... Rearrange SLP nodes with duplicate statements [PR98138]
16a39f8... RISC-V: Minimal support for Zimop extension.
d18d1a7... Fix Wstringop-overflow-47.c warning in RISC-V target.
7982b3f... RISC-V: Update .SAT_TRUNC dump check due to middle-end chan
f8512af... RISC-V: Fix typos in code
69ce456... RISC-V: Fix comment typos
a20c435... RISC-V: Fix format-diag warning from improperly formatted u
6c24404... RISC-V: Add deprecation warning to LP64E abi
5e106d5... RISC-V: Reject 'd' extension with ILP32E ABI
b9820a4... testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-a
11967b0... RISC-V: Improve length attributes for atomic insn sequences
b870cb8... RISC-V: Correct mode_idx attribute for viwalu wx variants [
b6a1ecd... RISC-V: NFC: Do not use zicond for pr105314 testcases
9bdf699... [target/116104] Fix more rtl-checking failures in ext-dce
0476f53... [PR rtl-optimization/116136] Fix previously latent SUBREG s
463bd56... RISC-V: Add configure check for B extention support
cbaa7b2... RISC-V: Add basic support for the Zacas extension
b2df229... RISC-V: Remove configure check for zabha
6bf3d45... RISC-V: Take Xmode instead of Pmode for ussub expanding
6ca3dab... [target/116104] Fix test guarding UINTVAL to extract shift
ed6d11c... [RISC-V][target/116085] Fix rv64 minmax extension avoidance
37cbd21... RISC-V: Work around bare apostrophe in error string.
7d22639... [PR rtl-optimization/116039] Fix life computation for promo
16d1997... [committed] Trivial testcase adjustment
13370bd... RISC-V: Error early with V and no M extension.
78e0cd7... RISC-V: Allow LICM hoist POLY_INT configuration code sequen
ecbda5a... [rtl-optimization/116037] Explicitly track if a destination
b95ba68... [PR rtl-optimization/115877][6/n] Add testcase from pr11587
bb13ddf... RISC-V: Fix snafu in SI mode splitters patch
bb7633d... [5/n][PR rtl-optimization/115877] Fix handling of input/out
eb6ee8d... RISC-V: Implement the .SAT_TRUNC for scalar
0d84f3d... [4/n][PR rtl-optimization/115877] Correct SUBREG handling i
7c7b6fd... [NFC][PR rtl-optimization/115877] Avoid setting irrelevant
cb6bdd5... RISC-V: Rearrange the test helper files for vector .SAT_*
1a05bff... [PR rtl-optimization/115877][2/n] Improve liveness computat
16ec691... [PR rtl-optimization/115877] Fix livein computation for ext
f2048cd... RISC-V: Fix testcase missing arch attribute
0af6332... Add debug counter for ext_dce
6e008e5... Fix liveness computation for shift/rotate counts in ext-dce
820041b... Revert "RISC-V: Attribute parser: Use alloca() instead of n
0315d0f... RISC-V: Allow adding enabled extension via target arch attr
9fb7957... RISC-V: Rewrite target attribute handling
894c444... RISC-V: Attribute parser: Use alloca() instead of new + std
25e37ab... RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark
5975c3c... RISC-V: Implement locality for __builtin_prefetch
ae8af3a... RISC-V: Add md files for vector BFloat16
21c85f9... RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
27cd96d... RISC-V: Add vector type of BFloat16 format
d38da39... [PR rtl-optimization/115876] Fix one of two ubsan reported
587dbc1... [RISC-V] Avoid unnecessary sign extension after memcmp
4939838... RISC-V: Disable misaligned vector access in hook riscv_slow
dd3171e... RISC-V: Add SiFive extensions, xsfvcp and xsfcease
2360e15... [to-be-committed,RISC-V] Eliminate unnecessary sign extensi
9996d07... RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
921baff... RISC-V: c implies zca, and conditionally zcf & zcd
bcb9efb... RISC-V: Update testsuite to use b
03d27d8... RISC-V: Add support for B standard extension
6add49f... RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form
c75ea60... RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form
3837405... [to-be-committed][RISC-V][V3] DCE analysis for extension el
34f337a... RISC-V: Implement .SAT_TRUNC for vector unsigned int
49d1922... [to-be-committed][v3][RISC-V] Handle bit manipulation of SI
cb9f4cb... [committed][RISC-V] Fix test expectations after recent late
db238f5... RISC-V: Describe -march behavior for dependent extensions
0d3084a... RISC-V: Add support for Zabha extension
9de4cfd... RISC-V: Fix asm check failure for truncated after SAT_SUB
2372ebb... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form
3eec935... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form
ea6cd7c... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form
8ab0fc4... RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form
8c274ac... [to-be-committed,RISC-V,V4] movmem for RISCV with V extensi
ad7bf69... RISC-V: Add testcases for vector truncate after .SAT_SUB
a81c09c... RISC-V: Update testcase comments to point to PSABI rather t
27edc62... RISC-V: Consolidate amo testcase variants
03bd609... RISC-V: Rename amo testcases
045a238... [committed][RISC-V] Fix expected output for thead store pai
856e74a... [PATCH v2 3/3] RISC-V: cmpmem for RISCV with V extension
8fe4247... ira: Scale save/restore costs of callee save registers with
711953c... [committed][RISC-V] Fix some of the testsuite fallout from
9595ea4... [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension
d73b645... RISC-V: Add dg-remove-option for z* extensions
e0b09c9... [committed][RISC-V][PR target/114139] Verify we have a CONS
14303d1... [PATCH v2] RISC-V: Remove integer vector eqne pattern
b5e20e7... [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well
0dc80ff... [RISC-V] Minor cleanup/improvement to bset/binv patterns
242fd71... [PATCH v2] RISC-V: Remove float vector eqne pattern
08e6be2... RISC-V: Promote Zaamo/Zalrsc to a when using an old binutil
d17f066... RISC-V: Add testcases for unsigned .SAT_SUB vector form 10
cb0263d... RISC-V: Add testcases for unsigned .SAT_SUB vector form 9
26dfa8d... RISC-V: Add testcases for unsigned .SAT_SUB vector form 8
25e2c84... RISC-V: Add testcases for unsigned .SAT_SUB vector form 7
756b296... RISC-V: Add testcases for unsigned .SAT_SUB vector form 6
17cf188... RISC-V: Add testcases for unsigned .SAT_SUB vector form 5
f5e626e... RISC-V: Add testcases for unsigned .SAT_SUB vector form 4
cf7d79d... RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
2059516... RISC-V: Add testcases for unsigned .SAT_ADD vector form 8
c518d08... RISC-V: Add testcases for unsigned .SAT_ADD vector form 7
d5fcee7... RISC-V: Add testcases for unsigned .SAT_ADD vector form 6
a663f2a... RISC-V: Add testcases for unsigned .SAT_ADD vector form 5
423d8f4... RISC-V: Add testcases for unsigned .SAT_ADD vector form 4
39d1cd1... RISC-V: Add testcases for unsigned .SAT_ADD vector form 3
0adc6ac... RISC-V: Add testcases for unsigned .SAT_ADD vector form 2
d7b67c6... RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12
e14ea14... RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11
6ba53a4... RISC-V: Move mode assertion out of conditional branch in em
6af88fe... RISC-V: Fix vwsll combine on rv32 targets
66ed10c... [committed] [RISC-V] Fix wrong patch application
26b47eb... [to-be-committed,RISC-V] Improve bset generation when bit p
f6010dc... [to-be-committed,RISC-V] Handle zero_extract destination fo
295193a... RISC-V: Add configure check for Zaamo/Zalrsc assembler supp
7bbf97d... [to-be-committed,RISC-V] Improve variable bit set for rv64
706f575... [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64
a2d509a... RISC-V: Add testcases for vector unsigned SAT_SUB form 2
a9cf5c3... RISC-V: Refine the SAT_ARITH test help header files [NFC]
13cd70e... RISC-V: Add testcases for scalar unsigned SAT_SUB form 10
6e34555... RISC-V: Add testcases for scalar unsigned SAT_SUB form 9
4b51d08... RISC-V: Add testcases for scalar unsigned SAT_SUB form 8
97bb64f... RISC-V: Add testcases for scalar unsigned SAT_SUB form 7
4118e84... RISC-V: Add testcases for scalar unsigned SAT_SUB form 6
b2ef770... RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
9e1054b... RISC-V: Add testcases for scalar unsigned SAT_SUB form 4
cf83fd6... RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
e29a44c... RISC-V: Add support for subword atomic loads/stores
fc63e04... Test: Move target independent test cases to gcc.dg/torture
5cccfbd... RISC-V: Allow any temp register to be used in amo tests
2dc7e9e... RISC-V: Fix amoadd call arguments
b50ec91... RISC-V: Move amo tests into subfolder
e22f75a... RISC-V: Add Zalrsc amo-op patterns
8bb23d6... RISC-V: Add Zalrsc and Zaamo testsuite support
67d574e... RISC-V: Add basic Zaamo and Zalrsc support
3f3aa24... RISC-V: Implement .SAT_SUB for unsigned vector int
dccad0a... [committed] [RISC-V] Drop dead round_32 test
643cf71... [to-be-committed] [RISC-V] Use bext for extracting a bit in
c904416... Just the testsuite bits from:
b8b0c02... [to-be-committed] [RISC-V] Use bext for extracting a bit in
b161ab4... FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14
52054a2... [committed] [RISC-V] Fix false-positive uninitialized varia
eaa49bf... [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of
5cce50e... RISC-V: Implement .SAT_SUB for unsigned scalar int
1c438d6... RISC-V: Add testcases for scalar unsigned SAT_ADD form 5
111ec5f... RISC-V: Add testcases for scalar unsigned SAT_ADD form 4
0dcdc91... RISC-V: Add testcases for scalar unsigned SAT_ADD form 3
3b2293c... RISC-V: Add testcases for scalar unsigned SAT_ADD form 2
49c1d6f... RISC-V: Add testcases for scalar unsigned SAT_ADD form 1
f91cea7... RISC-V: Regenerate opt urls.
fb44c71... Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) fo
8f726cf... RISC-V: Introduce -mvector-strict-align.
8fd618e... RISC-V: Add Zfbfmin extension
db3b669... Just the riscv bits from:
b188bc6... [to-be-committed] [RISC-V] Use Zbkb for general 64 bit cons
6a03105... RISC-V: Remove dead perm series code and document.
fe352bf... RISC-V: Add vector popcount, clz, ctz.
ef30a89... RISC-V: Add vandn combine helper.
17baa95... RISC-V: Use widening shift for scatter/gather if applicable
ae94f3f... RISC-V: Add vwsll combine helpers.
e1c7a5d... [to-be-committed] [RISC-V] Use pack to handle repeating con
5d05c1c... [to-be-committed] [RISC-V] Some basic patterns for zbkb cod
bf9c145... [to-be-committed][RISC-V] Reassociate constants in logical
f4e34b1... [to-be-committed] [RISC-V] Try inverting for constant synth
4e5987b... [to-be-committed][RISC-V] Generate nearby constant, then ad
52fc2ea... [committed] [v2] More logical op simplifications in simplif
ae6b8dd... [to-be-committed,v2,RISC-V] Use bclri in constant synthesis
778f806... RISC-V: Enable vectorization for vect-early-break_124-pr114
0de6d26... RISC-V: avoid LUI based const mat in alloca epilogue expans
fcb6eb4... RISC-V: avoid LUI based const mat in prologue/epilogue expa
5300baa... Regenerate riscv.opt.urls and i386.opt.urls
f623c17... DSE: Fix ICE after allow vector type in get_stored_val
9e17aea... [to-be-committed][RISC-V][PR target/115142] Do not create i
872f7ac... RISC-V: Implement -m{,no}fence-tso
7205845... [to-be-committed,RISC-V] Improve some shift-add sequences
a68bda6... RISC-V: Fix "Nan-box the result of movbf on soft-bf16"
55fe174... RISC-V: Modify _Bfloat16 to __bf16
afd3785... RISC-V: Implement IFN SAT_ADD for both the scalar and vecto
1db74cd... RISC-V: Add initial cost handling for segment loads/stores.
e8502a7... internal-fn: Do not force vcond_mask operands to reg.
46e4670... RISC-V: Cleanup some temporally files [NFC]
620d046... RISC-V: Enable vectorizable early exit testsuite
2e79d0c... RISC-V: Implement vectorizable early exit with vcond_mask_l
4950489... Vect: Support loop len in vectorizable early exit
ee2048d... Vect: Support new IFN SAT_ADD for unsigned vector int
4459be8... Internal-fn: Support new IFN SAT_ADD for unsigned scalar in
a64662d... RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi t
7f9bb38... RISC-V: Add Zvfbfwma extension to the -march= option
fa7e649... Add missing hunk in recent change.
aee0547... [v2,2/2] RISC-V: strcmp expansion: Use adjust_address() for
287d991... [v2,1/2] RISC-V: Add cmpmemsi expansion
c34c8a5... RISC-V: Test cbo.zero expansion for rv32
08b35b1... RISC-V: Allow by-pieces to do overlapping accesses in block
46e417c... RISC-V: add tests for overlapping mem ops
fdd84d4... RISC-V: Allow unaligned accesses in cpymemsi expansion
d261681... RISC-V: Add test cases for cpymem expansion
51d014d... [committed] Fix rv32 issues with recent zicboz work
ab30e41... [to-be-committed,RISC-V] Remove redundant AND in shift-add
75de89f... RISC-V: avoid LUI based const materialization ... [part of
d37e3c0... [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero
c409448... [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe
40e2b33... [1/3] expr: Export clear_by_pieces()
34117ea... RISC-V: Fix format issue for trailing operator [NFC]
8edd096... [to-be-committed,RISC-V] Improve AND with some constants
617f0fe... [to-be-committed,RISC-V] Improve single inverted bit extrac
f2873d2... [to-be-committed,RISC-V] Improve usage of slli.uw in consta
64b5767... [to-be-committed] RISC-V Fix minor regression in synthesis
bf7612c... [RISC-V] Use shNadd for constant synthesis
3b88790... RISC-V: Fix typos in code or comment [NFC]
abffcba... [committed] [RISC-V] Provide splitting guidance to combine
740cc62... RISC-V: Add tests for cpymemsi expansion
ea4dcc4... [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-
ad8a3dc... [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usag
e59953b... RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_exten
9a0bbee... RISC-V: Add zero_extract support for rv64gc
8ab5ebc... RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2
e8c481b... RISC-V: Add test for sraiw-31 special case
4de91ff... [committed][RISC-V] Turn on overlap_op_by_pieces for generi
e0c21fb... [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_
de46513... [RISC-V] [PATCH v2] Enable inlining str* by default
ac5d971... [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= op
0910786... RISC-V: Add testcase for PR114749.
88b251e... [RISC-V] Add support for _Bfloat16
fc3b1df... RISC-V: Document -mcmodel=large
484515d... So another constant synthesis improvement.
b8607b5... RISC-V: miscll comment fixes [NFC]
4b88d23... [committed][RISC-V] Fix nearbyint failure on rv32 and forma
f56b75e... [RFA][RISC-V] Improve constant synthesis for constants with
3a8e963... [committed] [RISC-V] Don't run new rounding tests on newlib
16129d7... [committed] [RISC-V] Trivial pattern cleanup
20d0403... [committed] [RISC-V] Fix detection of store pair fusion cas
f1e44c7... This is almost exclusively Jivan's work. His original post
8f21e07... RISC-V: Refine the condition for add additional vars in RVV
507b4e1... AVR: target/85624 - Use HImode for clrmemqi alignment. (*)
edf95a4... testsuite: Verify -fshort-enums and -fno-short-enums in pr3 (*)
5c1f687... testsuite: Add -fno-short-enums to pr97315-1.C (*)
345d145... testsuite: Add -fwrapv to signbit-5.c (*)
45a771d... i386: Fix some vex insns that prohibit egpr (*)
86dacfb... aarch64: Add another use of force_subreg [PR115464] (*)
32b2129... aarch64: Fix invalid nested subregs [PR115464] (*)
4e7735a... Move ix86_align_loops into a separate pass and insert the p (*)
ccca8df... Daily bump. (*)
63c51e0... c++/coroutines: fix passing *this to promise type, again [P (*)
d9bd361... [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests (*)
8c98f06... RISC-V: Make full-vec-move1.c test robust for optimization (*)
7268985... Daily bump. (*)
e903ada... s390: Fix high-level builtins vec_gfmsum{,_accum}_128 (*)
5a63e19... Daily bump. (*)
7d9bb37... Add -mcpu=power11 support. (*)
f688431... Daily bump. (*)
6bfd78c... Daily bump. (*)
534ffe7... Daily bump. (*)
6f1e687... Daily bump. (*)
b0dd13e... i386: Fix up __builtin_ia32_b{extr{,i}_u{32,64},zhi_{s,d}i} (*)
897cd79... Daily bump. (*)
9ca1d7a... AVR: target/116295 - Fix unrecognizable insn with __flash r (*)
a9255df... Daily bump. (*)
49e8eee... Daily bump. (*)
b1102f7... c++: alias and non-type template parm [PR116223] (*)
987fc81... c++: parse error with -std=c++14 -fconcepts [PR116071] (*)
ba26c47... hppa: Fix (plus (plus (mult (a) (mem_shadd_constant)) (b)) (*)
f2b5ca6... wide-int: Fix up mul_internal overflow checking [PR116224] (*)
3fe5720... libquadmath: Fix up libquadmath/math/sqrtq.c compilation in (*)
cad2693... fortran: Fix up pasto in gfc_get_array_descr_info (*)
ba45573... sh: Don't call make_insn_raw in sh_recog_treg_set_expr [PR1 (*)
c5ef3b9... Daily bump. (*)
de73898... compiler: panic arguments are empty interface type (*)
2405d29... libgomp: Remove bogus warnings from privatized-ref-2.f90. (*)
9906a98... Fortran: Suppress bogus used uninitialized warnings [PR1088 (*)
daced76... Update gcc fr.po (*)
eccf707... RISC-V: xtheadmemidx: Fix mode test for pre/post-modify add (*)
5103ee7... Daily bump. (*)
80a64e6... Daily bump. (*)
c386665... libstdc++: Fix __cpp_lib_chrono for old std::string ABI (*)
99eb84f... Daily bump. (*)
21e2d27... Update gcc .po files (*)
14fa2b2... forwprop: Don't add uses to dce list if debug statement [PR (*)
a295076... Refine constraint "Bk" to define_special_memory_constraint. (*)
30f4fa3... i386: Add non-optimize prefetchi intrins (*)
79d32ba... LoongArch: Remove gawk extension from a generator script. (*)
81db685... c++: generic lambda in default template argument [PR88313] (*)
37e54ff... c++: alias of alias tmpl with dependent attrs [PR115897] (*)
59e3934... libstdc++: fix uses of explicit object parameter [PR116038] (*)
241f710... c++: normalizing ttp constraints [PR115656] (*)
e548a88... c++: missing SFINAE during alias CTAD [PR115296] (*)
1287b4a... c++: prev declared hidden tmpl friend inst [PR112288] (*)
fb8da40... Daily bump. (*)
c637241... libstdc++: Add [[nodiscard]] to some std::locale functions (*)
c79e73e... libstdc++: Add missing constexpr to __atomic_impl::__clear_ (*)
8d52ae3... libstdc++: Initialize base in test allocator's constructor (*)
d8e5645... libstdc++: Fix std::tr2::dynamic_bitset shift operations [P (*)
a78480c... libstdc++: Remove std::basic_format_args default constructo (*)
85d07df... libstdc++: Make std::basic_format_context non-copyable [PR1 (*)
7d269e3... libstdc++: Make std::any_cast<void> ill-formed (LWG 3305) (*)
095be59... libstdc++: Define __cpp_lib_ranges in <algorithm> (*)
11b5ad5... libstdc++: Use direct-initialization for std::vector<bool>' (*)
5fcdb36... libstdc++: Use __glibcxx_ranges_as_const to guard P2278R4 c (*)
a1e1665... libstdc++: Use reserved form of [[__likely__]] in <variant> (*)
9ba75a6... libstdc++: Fix <ostream> and <istream> for -std=gnu++14 -fc (*)
ce84aba... libstdc++: Fix std::vector<bool> for -std=gnu++14 -fconcept (*)
973097d... i386: Fix up *<extract_type>_vinsert<shuffletype><extract_s (*)
fb2f72d... Bump BASE-VER. (*)
04696df... Update ChangeLog and version files for release (*)
0f4eb65... Daily bump. (*)
10323e2... Daily bump. (*)
ee6c5af... x86: Don't enable APX_F in 32-bit mode (*)
7c688e0... Daily bump. (*)
da7f0be... c++: wrong error initializing empty class [PR115900] (*)
a7f1b00... tree-optimization/116057 - wrong code with CCP and vector C (*)
61cb0c8... testsuite: Fix up consteval-prop21.C for 32-bit targets [PR (*)
9662299... c++: if consteval and consteval propagation [PR115583] (*)
56d5f8a... c++: consteval propagation and templates [PR115986] (*)
f30caf1... c++: ICE with concept, local class, and lambda [PR115561] (*)
98baaa1... Fix ICE with -fdump-tree-moref (*)
affb2e8... i386: Fix AVX512 intrin macro typo (*)
b858a51... Daily bump. (*)
c3eef3d... Daily bump. (*)
8eae5b0... Daily bump. (*)
92eb0ee... Daily bump. (*)
a32aff1... Regenerate gcc.pot (*)
a7f07e5... Daily bump. (*)
181f40f... testsuite: Fix up pr116034.c test for big/pdp endian [PR116 (*)
ab03866... RISC-V: Disable Zba optimization pattern if XTheadMemIdx is (*)
ae2909a... Daily bump. (*)
a544898... testsuite: Disable finite math only for test [PR115826] (*)
b41487a... libstdc++: Use [[maybe_unused]] attribute in src/c++23/prin (*)
5fad887... libstdc++: Do not use isatty on avr [PR115482] (*)
084768c... ssa: Fix up maybe_rewrite_mem_ref_base complex type handlin (*)
81f356f... i386: Change prefetchi output template (*)
109b389... [powerpc] [testsuite] reorder dg directives [PR106069] (*)
066c789... c++/coroutines: correct passing *this to promise type [PR10 (*)
50ff112... c++: xobj fn call without obj [PR115783] (*)
dfae324... Daily bump. (*)
9ddd5f8... Fix modref's iteraction with store merging (*)
bd535b4... rs6000: Catch unsupported ABI errors when using -mrop-prote (*)
35e5c2d... rs6000: Error on CPUs and ABIs that don't support the ROP p (*)
e2d746e... rs6000: ROP - Emit hashst and hashchk insns on Power8 and l (*)
33ebeb2... rs6000: Compute rop_hash_save_offset for non-Altivec compil (*)
c33532c... rs6000: Update ELFv2 stack frame comment showing the correc (*)
27ef3a0... Fix modref_eaf_analysis::analyze_ssa_name handling of value (*)
f2e9808... Fix accounting of offsets in unadjusted_ptr_and_unit_offset (*)
c5397d3... Compare loop bounds in ipa-icf (*)
9a7d668... Reduce recursive inlining of always_inline functions (*)
323d010... [PR115565] cse: Don't use a valid regno for non-register in (*)
91a6faf... Daily bump. (*)
043f3ad... Daily bump. (*)
bb34b7e... s390: Fix unresolved iterators bhfgq and xdee (*)
2eca8a9... Avoid undefined behaviour in build_option_suggestions (*)
94e4661... Revert "Fortran: Auto array allocation with function depend (*)
6b6a056... Daily bump. (*)
d15664f... Fortran: Fix wrong code in unlimited polymorphic assignment (*)
5034af8... Fortran: Auto array allocation with function dependencies [ (*)
1205104... rs6000: Fix .machine cpu selection w/ altivec [PR97367] (*)
ca0fa18... Fortran: character array constructor with >= 4 constant ele (*)
187eec8... Fix Xcode 16 build break with NULL != nullptr (*)
0abce41... RISC-V: Split vwadd.wx and vwsub.wx and add helpers. (*)
937713a... RISC-V: Do not allow v0 as dest when merging [PR115068]. (*)
3a7e796... RISC-V: Add -X to link spec (*)
92003fa... RISC-V: Fix parsing of Zic* extensions (*)
68ef0c3... RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar (*)
c38dbfc... RISC-V: Fix missing boolean_expression in zmmul extension (*)
4db3875... RISC-V: Bugfix vec_extract v mode iterator restriction mism (*)
87346ed... RISC-V: Bugfix vec_extract vls mode iterator restriction mi (*)
c32995c... [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_ (*)
2d7dda8... RISC-V: Use tu policy for first-element vec_set [PR115725]. (*)
b218c42... [RISC-V] add implied extension repeatly until stable (*)
a2a2916... Daily bump. (*)
493035c... eh: ICE with std::initializer_list and ASan [PR115865] (*)
747c4b5... Do not use caller-saved registers for COMDAT functions (*)
c314867... c++: ICE with __has_unique_object_representations [PR115476 (*)
a4c9ade... i386: PR target/115351: RTX costs for *concatditi3 and *ins (*)
b0452ed... analyzer: fix ICE seen with -fsanitize=undefined [PR114899] (*)
0b7ec50... Fix points_to_local_or_readonly_memory_p wrt TARGET_MEM_REF (*)
0f593e4... PR tree-optimization/113673: Avoid load merging when potent (*)
0fbad21... testsuite: Fix up builtin-clear-padding-3.c for -funsigned- (*)
f0c3a1c... c++/modules: Conditionally start timer during lazy load [PR (*)
4871b0f... Daily bump. (*)
1bbfe78... c++: constrained partial spec type context [PR111890] (*)
2249c63... c++: alias template with dependent attributes [PR115897] (*)
79c5a09... c++: bad 'this' conversion for nullary memfn [PR106760] (*)
3a963d4... alpha: Fix duplicate !tlsgd!62 assemble error [PR115526] (*)
01dfc5b... bitint: Use gsi_insert_on_edge rather than gsi_insert_on_ed (*)
d668f87... gimple-fold: Fix up __builtin_clear_padding lowering [PR115 (*)
297ea7e... c++: Fix ICE on constexpr placement new [PR115754] (*)
bf64404... vect: Merge loop mask and cond_op mask in fold-left reducti (*)
c58bede... tree-optimization/115868 - ICE with .MASK_CALL in simdclone (*)
5fad0b5... c++/modules: Propagate BINDING_VECTOR_*_DUPS_P on realloc [ (*)
4039c74... Daily bump. (*)
59ed01d... tree-optimization/115841 - reduction epilogue placement iss (*)
06829e5... tree-optimization/115843 - fix wrong-code with fully-masked (*)
e01012c... tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_ (*)
6f74a5f... tree-optimization/115701 - factor out maybe_duplicate_ssa_i (*)
ca275b6... tree-optimization/115867 - ICE with simdcall vectorization (*)
4a04110... Fixup unaligned load/store cost for znver5 (*)
d702a95... Fixup unaligned load/store cost for znver4 (*)
c8fdef7... [alpha] adjust MEM alignment for block move [PR115459] (*)
b3cff83... RISC-V: Allow adding enabled extension via target arch attr (*)
0e1f599... RISC-V: Rewrite target attribute handling (*)
b604d59... RISC-V: Fix comment/naming in attribute parsing code (*)
20fb450... RISC-V: Deduplicate arch subset list processing (*)
ea5907d... RISC-V: testsuite: Properly gate LTO tests (*)
7bc63f1... [i386] adjust flag_omit_frame_pointer in a single function (*)
102bcf1... [i386] restore recompute to override opts after change [PR1 (*)
1fff665... x86: Update branch hint for Redwood Cove. (*)
0fcadb3... Daily bump. (*)
71ec9ed... Fortran: improve attribute conflict checking [PR93635] (*)
13bfc38... Fix SSA_NAME leak due to def_stmt is removed before use_stm (*)
53dd1ce... Daily bump. (*)
c80a746... fortran: Assume there is no cyclic reference with submodule (*)
55988c4... fortran: Correctly evaluate scalar MASK arguments of MINLOC (*)
8197264... Daily bump. (*)
89f9342... LoongArch: TFmode is not allowed to be stored in the float (*)
5ade7af... s390: Fix output template for movv1qi (*)
cd11413... s390: Align *cjump_64 and *icjump_64 (*)
3cba6fb... Daily bump. (*)
d920658... libstdc++: Fix unwanted #pragma messages from PSTL headers (*)
21c8708... libstdc++: Fix std::to_array for trivial-ish types [PR11552 (*)
cff2707... RISC-V: NO_WARNING preferred else value for RVV (*)
29b2e1c... Fortran: Fix ICEs due to comp calls in initialization exprs (*)
d096ff3... Daily bump. (*)
b7a16ad... mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115 (*)
08c2abf... c++/modules: Keep entity mapping info across duplicate_decl (*)
ddea107... Daily bump. (*)
e7d81cf... testsuite: Align testcase with implementation [PR105090] (*)
47a8b46... middle-end: Fix stalled swapped condition code value [PR115 (*)
efa30f6... RISC-V: backport fix zcmp popretz [PR113715] (*)
76b4721... Daily bump. (*)
c94c8ff... libstdc++: Fix _Atomic(T) macro in <stdatomic.h> [PR115807] (*)
85a39a8... libstdc++: Define __glibcxx_assert_fail for non-verbose bui (*)
72753ec... Aarch64, bugfix: Fix NEON bigendian addp intrinsic [PR11489 (*)
83332e3... Arm: Fix ldrd offset range [PR115153] (*)
74c15cb... i386: Correct AVX10 CPUID emulation (*)
505382c... RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR1157 (*)
9d47a43... Daily bump. (*)
64a6c0d... tree-optimization/115723 - ICE with .COND_ADD reduction (*)
cde4119... tree-optimization/115694 - ICE with complex store rewrite (*)
03844a2... tree-optimization/115669 - fix SLP reduction association (*)
078cdcc... tree-optimization/115646 - ICE with pow shrink-wrapping fro (*)
c36acfe... Fortran: Unlimited polymorphic intrinsic function arguments (*)
a8617b5... Fix MinGW option -mcrtdll= (*)
a927d33... Daily bump. (*)
36ca07f... Fortran: fix associate with assumed-length character array (*)
3ab45a1... Daily bump. (*)
6c5ef49... RISC-V: fix internal error on global variable-length array (*)
7124ad8... Daily bump. (*)
100d353... Arm: Fix disassembly error in Thumb-1 relaxed load/store [P (*)
9f5620a... AVR: target/87376 - Use nop_general_operand for DImode inpu (*)
a633e41... Daily bump. (*)
dc63b5d... aarch64: PR target/115475 Implement missing __ARM_FEATURE_S (*)
1a97c8e... aarch64: PR target/115457 Implement missing __ARM_FEATURE_B (*)
1742b69... c++ frontend: check for missing condition for novector [PR1 (*)
0f71e52... Daily bump. (*)
6e1fb1f... Revert "Delete MALLOC_ABI_ALIGNMENT define from pa32-linux. (*)
acde9f8... hppa: Fix ICE caused by mismatched predicate and constraint (*)
3389a23... preprocessor: Create the parser before handling command-lin (*)
5574450... AVR: target/98762 - Handle partial clobber in movqi output. (*)
052f78d... rs6000: Fix wrong RTL patterns for vector merge high/low sh (*)
0e495e8... rs6000: Fix wrong RTL patterns for vector merge high/low ch (*)
88bfbab... Daily bump. (*)
8eb4695... aarch64: Fix typo in aarch64-ldp-fusion.cc:combine_reg_note (*)
5db1392... Daily bump. (*)
7249b3c... AVR: target/88236, target/115726 - Fix __memx code generati (*)
37bbd2c... c: Fix ICE related to incomplete structures in C23 [PR11493 (*)
78bd4b1... Daily bump. (*)
603b344... Fortran: fix ALLOCATE with SOURCE of deferred character len (*)
9f14748... Fortran: fix passing of optional dummy as actual to optiona (*)
b31e190... Fortran: fix for CHARACTER(len=*) dummies with bind(C) [PR1 (*)
4fe3fff... Daily bump. (*)
47cbc76... Daily bump. (*)
e6b115b... c++: decltype of capture proxy of ref [PR115504] (*)
a00a8d4... c++: alias CTAD and copy deduction guide [PR115198] (*)
33a9c4d... c++: using non-dep array var of unknown bound [PR115358] (*)
d5e352a... libstdc++: Fix std::format for chrono::duration with unsign (*)
ef8b60d... rs6000: Fix wrong RTL patterns for vector merge high/low wo (*)
15d304d... Daily bump. (*)
a8b77a6... libstdc++: Replace viewcvs links in docs with cgit links (*)
b70af0b... [libstdc++] [testsuite] defer to check_vect_support* [PR115 (*)
c2878a9... aarch64: Add support for -mcpu=grace (*)
6e6f10c... tree-ssa-pre.c/115214(ICE in find_or_generate_expression, a (*)
f9cc628... Daily bump. (*)
532357b... Daily bump. (*)
f91d9b3... libstdc++: Remove confusing text from status tables for rel (*)
b383719... Fix PR c/115587, uninitialized variable in c_parser_omp_loo (*)
4bf93fc... SPARC: fix internal error with -mv8plus on 64-bit Linux (*)
b7157f3... c-family: Add Warning property to Wnrvo option [PR115624] (*)
faf5994... Daily bump. (*)
2b5e8f9... rs6000: Don't clobber return value when eh_return called [P (*)
1a2329d... Daily bump. (*)
1735b86... Daily bump. (*)
70d9d92... Daily bump. (*)
9421f02... AArch64: Fix cpu features initialization [PR115342] (*)
a851931... libstdc++: Fix test on x86_64 and non-simd targets (*)
a16f47f... Build: Set gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips (*)
272e8c9... tree-optimization/115278 - fix DSE in if-conversion wrt vol (*)
65e2586... tree-optimization/115508 - fix ICE with SLP scheduling and (*)
85d32e6... Avoid SLP_REPRESENTATIVE access for VEC_PERM in SLP schedul (*)
30fca2c... Daily bump. (*)
e77f314... libstdc++: Fix find_last_set(simd_mask) to ignore padding b (*)
d26fa1c... vshuf-mem.C: Make -march=z14 depend on s390_vxe (*)
b4e4997... testsuite: Add -Wno-psabi to vshuf-mem.C test (*)
166c9f9... IBM Z: Fix ICE in expand_perm_as_replicate (*)
f79e909... bitint: Fix up lowering of COMPLEX_EXPR [PR115544] (*)
74a58c3... diagnostics: Fix add_misspelling_candidates [PR115440] (*)
946f26e... Daily bump. (*)
6f6103c... Daily bump. (*)
789f055... Daily bump. (*)
9226487... c-family: Fix -Warray-compare warning ICE [PR115290] (*)
5be6d9d... c++: Fix up floating point conversion rank comparison for _ (*)
20cda2e... c++: undeclared identifier in requires-clause [PR99678] (*)
4df8640... c++: ICE w/ ambig and non-strictly-viable cands [PR115239] (*)
9583f78... c++: visibility wrt concept-id as targ [PR115283] (*)
0ed63e3... s390: testsuite: Fix ifcvt-one-insn-bool.c (*)
8f124e6... s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR1095 (*)
13a09f3... Daily bump. (*)
a4f8e9e... Daily bump. (*)
3fe255f... riscv: Allocate enough space to strcpy() string (*)
6b2fc15... Daily bump. (*)
75251f5... libstdc++: Fix declaration of posix_memalign for freestandi (*)
b740c09... Daily bump. (*)
8bd6e40... Daily bump. (*)
7593dae... arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR11 (*)
9100e78... testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115 (*)
a657148... arm: Zero/Sign extends for CMSE security on Armv8-M.baselin (*)
dfc5c98... Daily bump. (*)
e6b1c08... Fix building JIT with musl libc [PR115442] (*)
7d64bc0... ira: Fix go_through_subreg offset calculation [PR115281] (*)
60e4cc3... Daily bump. (*)
ff8105b... c++: lambda in pack expansion [PR115378] (*)
b5ad443... Fix crash on access-to-incomplete type (*)
72a59a1... Add testcase for PR ada/114398 (*)
a1bec04... ada: Storage_Error in indirect call to function returning l (*)
6bd8a3a... libgcc/aarch64: also provide AT_HWCAP2 fallback (*)
489b58b... libstdc++: Fix simd<char> conversion for -fno-signed-char f (*)
237f060... libstdc++: Avoid MMX return types from __builtin_shufflevec (*)
ff46467... libstdc++: Use __builtin_shufflevector for simd split and c (*)
affb4f3... Daily bump. (*)
2ceab88... Daily bump. (*)
c3e16ed... Fortran: fix ALLOCATE with SOURCE=, zero-length character [ (*)
96f9b06... Daily bump. (*)
ca19249... arm: Fix CASE_VECTOR_SHORTEN_MODE for thumb2. (*)
0f616e7... bitint: Fix up lower_addsub_overflow [PR115352] (*)
7d40974... Daily bump. (*)
56c7372... c: Fix up pointer types to may_alias structures [PR114493] (*)
35ed54f... aarch64: Add missing ACLE macro for NEON-SVE Bridge (*)
d576034... Daily bump. (*)
e11a42b... testsuite: i386: Require ifunc support in gcc.target/i386/a (*)
7f0f88e... Daily bump. (*)
c6e6258... libstdc++: Only define std::span::at for C++26 [PR115335] (*)
a88e13b... fold-const: Fix up CLZ handling in tree_call_nonnegative_wa (*)
f9af4a0... builtins: Force SAVE_EXPR for __builtin_{add,sub,mul}_overf (*)
1c1bc25... invoke.texi: Clarify -march=lujiazui (*)
a7dd44c... rs6000: Fix up PCH in --enable-host-pie builds [PR115324] (*)
14a7296... combine: Fix up simplify_compare_const [PR115092] (*)
e805232... testsuite: gm2: Remove timeout overrides [PR114886] (*)
d92b508... libstdc++: Build libbacktrace and 19_diagnostics/stacktrace (*)
b2bbf98... Daily bump. (*)
955202e... libstdc++: Fix -Wstringop-overflow warning coming from std: (*)
97474ba... Add AVX10.1 target_clones support (*)
1dbf796... Daily bump. (*)
a31676a... Daily bump. (*)
d7f4279... AVR: target/115317 - Make isinf(-Inf) return -1. (*)
2f097c0... libstdc++: Replace link to gcc-4.3.2 docs in manual [PR1152 (*)
9d08c55... AVR: tree-optimization/115307 - Work around isinf bloat fro (*)
5ca4e16... Daily bump. (*)
ec92744... alpha: Fix invalid RTX in divmodsi insn patterns [PR115297] (*)
36575f5... vect: Fix access size alignment assumption [PR115192] (*)
cd161b3... i386: Fix ix86_option override after change [PR 113719] (*)
06333a1... Daily bump. (*)
201cfa7... MIPS16: Mark $2/$3 as clobbered if GP is used (*)
8f6c56c... Daily bump. (*)
fba2843... Fix link failure of GNAT tools on 32-bit SPARC/Linux (*)
90a4476... tree-optimization/115149 - VOP live and missing PHIs (*)
2a1fdd5... tree-optimization/115197 - fix ICE w/ constant in LC PHI an (*)
9e971c6... tree-optimization/114921 - _Float16 -> __bf16 isn't noop fi (*)
b4d4ece... Align tight&hot loop without considering max skipping bytes (*)
8060035... Adjust generic loop alignment from 16:11:8 to 16 for Intel (*)
e2b66da... Daily bump. (*)
dbeb3d1... Fortran: Fix SHAPE for zero-size arrays (*)
89dff14... libstdc++: Guard use of sized deallocation [PR114940] (*)
e78980f... LoongArch: Guard REGNO with REG_P in loongarch_expand_condi (*)
133da68... Daily bump. (*)
4790076... tree-optimization/115232 - demangle failure during -Waccess (*)
0cae44a... Daily bump. (*)
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