https://gcc.gnu.org/g:71db6b9e2fdff223f757c52a602e833a652244e0
commit 71db6b9e2fdff223f757c52a602e833a652244e0
Author: Michael Meissner <meiss...@linux.ibm.com>
Date:   Fri Aug 2 20:47:42 2024 -0400

    Revert changes

Diff:
---
 gcc/config/rs6000/power10.md        | 144 ++++++++++++++++++------------------
 gcc/config/rs6000/rs6000-arch.def   |   1 -
 gcc/config/rs6000/rs6000-c.cc       |   2 -
 gcc/config/rs6000/rs6000-cpus.def   |   3 -
 gcc/config/rs6000/rs6000-opts.h     |   1 -
 gcc/config/rs6000/rs6000-tables.opt |  11 +--
 gcc/config/rs6000/rs6000.cc         |  34 ++-------
 gcc/config/rs6000/rs6000.h          |   1 -
 gcc/config/rs6000/rs6000.md         |   2 +-
 9 files changed, 85 insertions(+), 114 deletions(-)

diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index e42b057dc45b..2310c4603457 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,4 @@
-;; Scheduling description for the IBM Power10, Power11, and Future processors.
+;; Scheduling description for the IBM Power10 and Power11 processors.
 ;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
 ;;
 ;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +97,12 @@
        (eq_attr "update" "no")
        (eq_attr "size" "!128")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-fused-load" 4
   (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@
        (eq_attr "update" "no")
        (eq_attr "size" "!128")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-load-update" 4
   (and (eq_attr "type" "load")
        (eq_attr "update" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@
        (eq_attr "update" "no")
        (eq_attr "size" "64")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 (define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@
        (eq_attr "update" "no")
        (eq_attr "size" "64")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-double" 4
   (and (eq_attr "type" "fpload")
        (eq_attr "update" "yes")
        (eq_attr "size" "64")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@
   (and (eq_attr "type" "fpload")
        (eq_attr "update" "no")
        (eq_attr "size" "32")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10")
 
 (define_insn_reservation "power10-fpload-update-single" 7
   (and (eq_attr "type" "fpload")
        (eq_attr "update" "yes")
        (eq_attr "size" "32")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-vecload" 4
   (and (eq_attr "type" "vecload")
        (eq_attr "size" "!256")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 ; lxvp
 (define_insn_reservation "power10-vecload-pair" 4
   (and (eq_attr "type" "vecload")
        (eq_attr "size" "256")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 ; Store Unit
@@ -178,12 +178,12 @@
        (eq_attr "prefixed" "no")
        (eq_attr "size" "!128")
        (eq_attr "size" "!256")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-store" 0
   (and (eq_attr "type" "fused_store_store")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 (define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@
        (eq_attr "prefixed" "yes")
        (eq_attr "size" "!128")
        (eq_attr "size" "!256")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 ; Update forms have 2 cycle latency for updated addr reg
 (define_insn_reservation "power10-store-update" 2
   (and (eq_attr "type" "store,fpstore")
        (eq_attr "update" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_power10")
 
 ; stxvp
 (define_insn_reservation "power10-vecstore-pair" 0
   (and (eq_attr "type" "vecstore")
        (eq_attr "size" "256")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,stu0_power10+stu1_power10")
 
 (define_insn_reservation "power10-larx" 4
   (and (eq_attr "type" "load_l")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,LU_power10")
 
 ; All load quad forms
 (define_insn_reservation "power10-lq" 4
   (and (eq_attr "type" "load,load_l")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,LU_power10+SXU_power10")
 
 (define_insn_reservation "power10-stcx" 0
   (and (eq_attr "type" "store_c")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_power10")
 
 ; All store quad forms
 (define_insn_reservation "power10-stq" 0
   (and (eq_attr "type" "store,store_c")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,stu0_power10+stu1_power10")
 
 (define_insn_reservation "power10-sync" 1
   (and (eq_attr "type" "sync,isync")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 
@@ -248,7 +248,7 @@
 (define_insn_reservation "power10-alu" 2
   (and (eq_attr "type" "add,exts,integer,logical,isel")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 ; 4 cycle CR latency
 (define_bypass 4 "power10-alu"
@@ -256,28 +256,28 @@
 
 (define_insn_reservation "power10-fused_alu" 2
   (and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 ; paddi
 (define_insn_reservation "power10-paddi" 2
   (and (eq_attr "type" "add")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 ; Rotate/shift (non-record form)
 (define_insn_reservation "power10-rot" 2
   (and (eq_attr "type" "insert,shift")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 ; Record form rotate/shift
 (define_insn_reservation "power10-rot-compare" 3
   (and (eq_attr "type" "insert,shift")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 ; 5 cycle CR latency
 (define_bypass 5 "power10-rot-compare"
@@ -285,7 +285,7 @@
 
 (define_insn_reservation "power10-alu2" 3
   (and (eq_attr "type" "cntlz,popcnt,trap")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 ; 5 cycle CR latency
 (define_bypass 5 "power10-alu2"
@@ -293,24 +293,24 @@
 
 (define_insn_reservation "power10-cmp" 2
   (and (eq_attr "type" "cmp")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 ; Treat 'two' and 'three' types as 2 or 3 way cracked
 (define_insn_reservation "power10-two" 4
   (and (eq_attr "type" "two")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-three" 6
   (and (eq_attr "type" "three")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_all_power10,EXU_power10")
 
 (define_insn_reservation "power10-mul" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 ; 4 cycle MUL->MUL latency
 (define_bypass 4 "power10-mul"
@@ -319,7 +319,7 @@
 (define_insn_reservation "power10-mul-compare" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 ; 4 cycle MUL->MUL latency
 (define_bypass 4 "power10-mul-compare"
@@ -331,13 +331,13 @@
 (define_insn_reservation "power10-div" 12
   (and (eq_attr "type" "div")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-div-compare" 12
   (and (eq_attr "type" "div")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 ; 14 cycle CR latency
 (define_bypass 14 "power10-div-compare"
@@ -345,34 +345,34 @@
 
 (define_insn_reservation "power10-crlogical" 2
   (and (eq_attr "type" "cr_logical")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfcrf" 2
   (and (eq_attr "type" "mfcrf")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfcr" 3
   (and (eq_attr "type" "mfcr")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 ; Should differentiate between 1 cr field and > 1 since target of > 1 cr
 ; is cracked
 (define_insn_reservation "power10-mtcr" 3
   (and (eq_attr "type" "mtcr")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mtjmpr" 3
   (and (eq_attr "type" "mtjmpr")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfjmpr" 2
   (and (eq_attr "type" "mfjmpr")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 
@@ -380,126 +380,126 @@
 
 (define_insn_reservation "power10-fpsimple" 3
   (and (eq_attr "type" "fpsimple")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-fp" 5
   (and (eq_attr "type" "fp,dmul")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-fpcompare" 3
   (and (eq_attr "type" "fpcompare")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-sdiv" 22
   (and (eq_attr "type" "sdiv")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-ddiv" 27
   (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-sqrt" 26
   (and (eq_attr "type" "ssqrt")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-dsqrt" 36
   (and (eq_attr "type" "dsqrt")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vec-2cyc" 2
   (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-fused-vec" 2
   (and (eq_attr "type" "fused_vector")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-veccmp" 3
   (and (eq_attr "type" "veccmp")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecsimple" 2
   (and (eq_attr "type" "vecsimple")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecnormal" 5
   (and (eq_attr "type" "vecfloat,vecdouble")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-qp" 12
   (and (eq_attr "type" "vecfloat,vecdouble")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecperm" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "prefixed" "no")
        (eq_attr "dot" "no")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecperm-compare" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "dot" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-prefixed-vecperm" 3
   (and (eq_attr "type" "vecperm")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 (define_insn_reservation "power10-veccomplex" 6
   (and (eq_attr "type" "veccomplex")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecfdiv" 24
   (and (eq_attr "type" "vecfdiv")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-vecdiv" 27
   (and (eq_attr "type" "vecdiv")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-qpdiv" 56
   (and (eq_attr "type" "vecdiv")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-qpmul" 24
   (and (eq_attr "type" "qmul")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mtvsr" 2
   (and (eq_attr "type" "mtvsr")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-mfvsr" 2
   (and (eq_attr "type" "mfvsr")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 
@@ -507,26 +507,26 @@
 ; Branch is 2 cycles, grouped with STU for issue
 (define_insn_reservation "power10-branch" 2
   (and (eq_attr "type" "jmpreg,branch")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,STU_power10")
 
 (define_insn_reservation "power10-fused-branch" 3
   (and (eq_attr "type" "fused_mtbc")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,STU_power10")
 
 
 ; Crypto
 (define_insn_reservation "power10-crypto" 4
   (and (eq_attr "type" "crypto")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 
 ; HTM
 (define_insn_reservation "power10-htm" 2
   (and (eq_attr "type" "htmsimple,htm")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 
@@ -535,26 +535,26 @@
 (define_insn_reservation "power10-dfp" 12
   (and (eq_attr "type" "dfp")
        (eq_attr "size" "!128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_power10")
 
 (define_insn_reservation "power10-dfpq" 12
   (and (eq_attr "type" "dfp")
        (eq_attr "size" "128")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_power10")
 
 ; MMA
 (define_insn_reservation "power10-mma" 9
   (and (eq_attr "type" "mma")
        (eq_attr "prefixed" "no")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_any_power10,EXU_super_power10")
 
 (define_insn_reservation "power10-prefixed-mma" 9
   (and (eq_attr "type" "mma")
        (eq_attr "prefixed" "yes")
-       (eq_attr "cpu" "power10,power11,future"))
+       (eq_attr "cpu" "power10,power11"))
   "DU_even_power10,EXU_super_power10")
 ; 4 cycle MMA->MMA latency
 (define_bypass 4 "power10-mma,power10-prefixed-mma"
diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index d103c57867a1..e5b6e9581331 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -46,4 +46,3 @@ ARCH_EXPAND(POWER8,  "power8")
 ARCH_EXPAND(POWER9,  "power9")
 ARCH_EXPAND(POWER10, "power10")
 ARCH_EXPAND(POWER11, "power11")
-ARCH_EXPAND(FUTURE,  "future")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 82826f96a8e7..c8f33289fa38 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -440,8 +440,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
   if ((arch_flags & ARCH_MASK_POWER11) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
-  if ((arch_flags & ARCH_MASK_FUTURE) != 0)
-    rs6000_define_or_undefine_macro (define_p, "_ARCH_FUTURE");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index e73d9ef51f8d..a3568898b0b6 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,8 +86,6 @@
 
 #define POWER11_MASKS_SERVER   ISA_3_1_MASKS_SERVER
 
-#define FUTURE_MASKS_SERVER    POWER11_MASKS_SERVER
-
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX    \
                                 | OPTION_MASK_FLOAT128_KEYWORD         \
@@ -251,7 +249,6 @@ RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | 
ISA_3_0_MASKS_SERVER
            | OPTION_MASK_HTM)
 RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | 
ISA_3_1_MASKS_SERVER)
 RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | 
POWER11_MASKS_SERVER)
-RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | FUTURE_MASKS_SERVER)
 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
            | MASK_POWERPC64)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index c25ddf92858c..88e357835a5c 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -63,7 +63,6 @@ enum processor_type
    PROCESSOR_POWER9,
    PROCESSOR_POWER10,
    PROCESSOR_POWER11,
-   PROCESSOR_FUTURE,
 
    PROCESSOR_RS64A,
    PROCESSOR_MPCCORE,
diff --git a/gcc/config/rs6000/rs6000-tables.opt 
b/gcc/config/rs6000/rs6000-tables.opt
index fc187c641f8d..a5649fef1ece 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -189,17 +189,14 @@ EnumValue
 Enum(rs6000_cpu_opt_value) String(power11) Value(53)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(future) Value(54)
+Enum(rs6000_cpu_opt_value) String(powerpc) Value(54)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc) Value(55)
+Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64) Value(56)
+Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56)
 
 EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(57)
-
-EnumValue
-Enum(rs6000_cpu_opt_value) String(rs64) Value(58)
+Enum(rs6000_cpu_opt_value) String(rs64) Value(57)
 
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 170ebc4384a9..12d9b11de006 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1067,7 +1067,7 @@ struct processor_costs power9_cost = {
   COSTS_N_INSNS (3),   /* SF->DF convert */
 };
 
-/* Instruction costs on Power10/Power11/future processors.  */
+/* Instruction costs on Power10/Power11 processors.  */
 static const
 struct processor_costs power10_cost = {
   COSTS_N_INSNS (2),   /* mulsi */
@@ -1836,15 +1836,10 @@ get_arch_flags (int cpu_index)
   const HOST_WIDE_INT ARCH_COMBO_POWER9  = ARCH_MASK_POWER9  | 
ARCH_COMBO_POWER8;
   const HOST_WIDE_INT ARCH_COMBO_POWER10 = ARCH_MASK_POWER10 | 
ARCH_COMBO_POWER9;
   const HOST_WIDE_INT ARCH_COMBO_POWER11 = ARCH_MASK_POWER11 | 
ARCH_COMBO_POWER10;
-  const HOST_WIDE_INT ARCH_COMBO_FUTURE  = ARCH_MASK_FUTURE  | 
ARCH_COMBO_POWER11;
 
   if (cpu_index >= 0)
     switch (processor_target_table[cpu_index].processor)
       {
-      case PROCESSOR_FUTURE:
-       ret = ARCH_COMBO_FUTURE;
-       break;
-
       case PROCESSOR_POWER11:
        ret = ARCH_COMBO_POWER11;
        break;
@@ -4436,8 +4431,7 @@ rs6000_option_override_internal (bool global_init_p)
   if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
     {
       if (rs6000_tune == PROCESSOR_POWER10
-         || rs6000_tune == PROCESSOR_POWER11
-         || rs6000_tune == PROCESSOR_FUTURE)
+         || rs6000_tune == PROCESSOR_POWER11)
        rs6000_isa_flags |= OPTION_MASK_P10_FUSION;
       else
        rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION;
@@ -4468,7 +4462,6 @@ rs6000_option_override_internal (bool global_init_p)
                        && rs6000_tune != PROCESSOR_POWER9
                        && rs6000_tune != PROCESSOR_POWER10
                        && rs6000_tune != PROCESSOR_POWER11
-                       && rs6000_tune != PROCESSOR_FUTURE
                        && rs6000_tune != PROCESSOR_PPCA2
                        && rs6000_tune != PROCESSOR_CELL
                        && rs6000_tune != PROCESSOR_PPC476);
@@ -4484,7 +4477,6 @@ rs6000_option_override_internal (bool global_init_p)
                                 || rs6000_tune == PROCESSOR_POWER9
                                 || rs6000_tune == PROCESSOR_POWER10
                                 || rs6000_tune == PROCESSOR_POWER11
-                                || rs6000_tune == PROCESSOR_FUTURE
                                 || rs6000_tune == PROCESSOR_PPCE500MC
                                 || rs6000_tune == PROCESSOR_PPCE500MC64
                                 || rs6000_tune == PROCESSOR_PPCE5500
@@ -4785,7 +4777,6 @@ rs6000_option_override_internal (bool global_init_p)
 
       case PROCESSOR_POWER10:
       case PROCESSOR_POWER11:
-      case PROCESSOR_FUTURE:
        rs6000_cost = &power10_cost;
        break;
 
@@ -5959,8 +5950,6 @@ rs6000_machine_from_flags (void)
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
             | OPTION_MASK_ALTIVEC);
 
-  if ((arch_flags & ARCH_MASK_FUTURE) != 0)
-    return "future";
   if ((arch_flags & ARCH_MASK_POWER11) != 0)
     return "power11";
   if ((arch_flags & ARCH_MASK_POWER10) != 0)
@@ -10212,7 +10201,6 @@ rs6000_reassociation_width (unsigned int opc 
ATTRIBUTE_UNUSED,
     case PROCESSOR_POWER9:
     case PROCESSOR_POWER10:
     case PROCESSOR_POWER11:
-    case PROCESSOR_FUTURE:
       if (DECIMAL_FLOAT_MODE_P (mode))
        return 1;
       if (VECTOR_MODE_P (mode))
@@ -18300,8 +18288,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, 
rtx_insn *dep_insn, int cost,
        /* Separate a load from a narrower, dependent store.  */
        if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
             || rs6000_tune == PROCESSOR_POWER10
-            || rs6000_tune == PROCESSOR_POWER11
-            || rs6000_tune == PROCESSOR_FUTURE)
+            || rs6000_tune == PROCESSOR_POWER11)
            && GET_CODE (PATTERN (insn)) == SET
            && GET_CODE (PATTERN (dep_insn)) == SET
            && MEM_P (XEXP (PATTERN (insn), 1))
@@ -18341,7 +18328,6 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, 
rtx_insn *dep_insn, int cost,
                 || rs6000_tune == PROCESSOR_POWER9
                 || rs6000_tune == PROCESSOR_POWER10
                 || rs6000_tune == PROCESSOR_POWER11
-                || rs6000_tune == PROCESSOR_FUTURE
                  || rs6000_tune == PROCESSOR_CELL)
                 && recog_memoized (dep_insn)
                 && (INSN_CODE (dep_insn) >= 0))
@@ -18917,7 +18903,6 @@ rs6000_issue_rate (void)
     return 6;
   case PROCESSOR_POWER10:
   case PROCESSOR_POWER11:
-  case PROCESSOR_FUTURE:
     return 8;
   default:
     return 1;
@@ -19633,11 +19618,10 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, 
int sched_verbose,
   if (rs6000_tune == PROCESSOR_POWER6)
     load_store_pendulum = 0;
 
-  /* Do Power10/Power11/future dependent reordering.  */
+  /* Do Power10/Power11 dependent reordering.  */
   if (last_scheduled_insn
       && (rs6000_tune == PROCESSOR_POWER10
-         || rs6000_tune == PROCESSOR_POWER11
-         || rs6000_tune == PROCESSOR_FUTURE))
+         || rs6000_tune == PROCESSOR_POWER11))
     power10_sched_reorder (ready, n_ready - 1);
 
   return rs6000_issue_rate ();
@@ -19661,11 +19645,10 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, 
rtx_insn **ready,
       && recog_memoized (last_scheduled_insn) >= 0)
     return power9_sched_reorder2 (ready, *pn_ready - 1);
 
-  /* Do Power10/Power11/future dependent reordering.  */
+  /* Do Power10/Power11 dependent reordering.  */
   if (last_scheduled_insn
       && (rs6000_tune == PROCESSOR_POWER10
-         || rs6000_tune == PROCESSOR_POWER11
-         || rs6000_tune == PROCESSOR_FUTURE))
+         || rs6000_tune == PROCESSOR_POWER11))
     return power10_sched_reorder (ready, *pn_ready - 1);
 
   return cached_can_issue_more;
@@ -22883,8 +22866,7 @@ rs6000_register_move_cost (machine_mode mode,
                 out to be a nop.  */
              if (rs6000_tune == PROCESSOR_POWER9
                  || rs6000_tune == PROCESSOR_POWER10
-                 || rs6000_tune == PROCESSOR_POWER11
-                 || rs6000_tune == PROCESSOR_FUTURE)
+                 || rs6000_tune == PROCESSOR_POWER11)
                ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
              else
                ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index cbb2d0632981..14dc66676c1b 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -531,7 +531,6 @@ extern int rs6000_vector_align[];
 #define TARGET_POWER9          ((rs6000_arch_flags & ARCH_MASK_POWER9)  != 0)
 #define TARGET_POWER10         ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
 #define TARGET_POWER11         ((rs6000_arch_flags & ARCH_MASK_POWER11) != 0)
-#define TARGET_FUTURE          ((rs6000_arch_flags & ARCH_MASK_FUTURE)  != 0)
 
 /* In the past we represented power8, power10 as an ISA bit and used internal
    switches the user was not supposed to use for -mpower8-internal and
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5722a67f9699..0524cf8ee6f3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -350,7 +350,7 @@
    ppc750,ppc7400,ppc7450,
    ppc403,ppc405,ppc440,ppc476,
    ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
-   power4,power5,power6,power7,power8,power9,power10,power11,future,
+   power4,power5,power6,power7,power8,power9,power10,power11,
    rs64a,mpccore,cell,ppca2,titan"
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))

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