https://gcc.gnu.org/g:a489eddc49baf526a4ddbef6f40cd8f31af0529a
commit a489eddc49baf526a4ddbef6f40cd8f31af0529a
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Aug 2 18:16:22 2024 -0400
Add support for -mcpu=future
This patch adds the support that can be used in developing GCC support for
future PowerPC processors.
2024-08-02 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000-arch.def: Add future processor.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(future cpu): Add support for -mcpu=future.
* config/rs6000/rs6000-opts.h (enum processor_type): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (get_arch_flags): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_register_move_cost): Likewise.
* config/rs6000/rs6000.h (TARGET_FUTURE): New macro.
* config/rs6000/rs6000.md (cpu attribute): Add future processor.
Diff:
---
gcc/config/rs6000/rs6000-arch.def | 1 +
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 3 +++
gcc/config/rs6000/rs6000-opts.h | 1 +
gcc/config/rs6000/rs6000-tables.opt | 11 +++++++----
gcc/config/rs6000/rs6000.cc | 34 ++++++++++++++++++++++++++--------
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
8 files changed, 42 insertions(+), 13 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-arch.def
b/gcc/config/rs6000/rs6000-arch.def
index e5b6e9581331..d103c57867a1 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -46,3 +46,4 @@ ARCH_EXPAND(POWER8, "power8")
ARCH_EXPAND(POWER9, "power9")
ARCH_EXPAND(POWER10, "power10")
ARCH_EXPAND(POWER11, "power11")
+ARCH_EXPAND(FUTURE, "future")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index c8f33289fa38..82826f96a8e7 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -440,6 +440,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags,
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
if ((arch_flags & ARCH_MASK_POWER11) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
+ if ((arch_flags & ARCH_MASK_FUTURE) != 0)
+ rs6000_define_or_undefine_macro (define_p, "_ARCH_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index a3568898b0b6..e73d9ef51f8d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,6 +86,8 @@
#define POWER11_MASKS_SERVER ISA_3_1_MASKS_SERVER
+#define FUTURE_MASKS_SERVER POWER11_MASKS_SERVER
+
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -249,6 +251,7 @@ RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 |
ISA_3_0_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 |
ISA_3_1_MASKS_SERVER)
RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 |
POWER11_MASKS_SERVER)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | FUTURE_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
| MASK_POWERPC64)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 88e357835a5c..c25ddf92858c 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -63,6 +63,7 @@ enum processor_type
PROCESSOR_POWER9,
PROCESSOR_POWER10,
PROCESSOR_POWER11,
+ PROCESSOR_FUTURE,
PROCESSOR_RS64A,
PROCESSOR_MPCCORE,
diff --git a/gcc/config/rs6000/rs6000-tables.opt
b/gcc/config/rs6000/rs6000-tables.opt
index a5649fef1ece..fc187c641f8d 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -189,14 +189,17 @@ EnumValue
Enum(rs6000_cpu_opt_value) String(power11) Value(53)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc) Value(54)
+Enum(rs6000_cpu_opt_value) String(future) Value(54)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55)
+Enum(rs6000_cpu_opt_value) String(powerpc) Value(55)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56)
+Enum(rs6000_cpu_opt_value) String(powerpc64) Value(56)
EnumValue
-Enum(rs6000_cpu_opt_value) String(rs64) Value(57)
+Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(57)
+
+EnumValue
+Enum(rs6000_cpu_opt_value) String(rs64) Value(58)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 12d9b11de006..170ebc4384a9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1067,7 +1067,7 @@ struct processor_costs power9_cost = {
COSTS_N_INSNS (3), /* SF->DF convert */
};
-/* Instruction costs on Power10/Power11 processors. */
+/* Instruction costs on Power10/Power11/future processors. */
static const
struct processor_costs power10_cost = {
COSTS_N_INSNS (2), /* mulsi */
@@ -1836,10 +1836,15 @@ get_arch_flags (int cpu_index)
const HOST_WIDE_INT ARCH_COMBO_POWER9 = ARCH_MASK_POWER9 |
ARCH_COMBO_POWER8;
const HOST_WIDE_INT ARCH_COMBO_POWER10 = ARCH_MASK_POWER10 |
ARCH_COMBO_POWER9;
const HOST_WIDE_INT ARCH_COMBO_POWER11 = ARCH_MASK_POWER11 |
ARCH_COMBO_POWER10;
+ const HOST_WIDE_INT ARCH_COMBO_FUTURE = ARCH_MASK_FUTURE |
ARCH_COMBO_POWER11;
if (cpu_index >= 0)
switch (processor_target_table[cpu_index].processor)
{
+ case PROCESSOR_FUTURE:
+ ret = ARCH_COMBO_FUTURE;
+ break;
+
case PROCESSOR_POWER11:
ret = ARCH_COMBO_POWER11;
break;
@@ -4431,7 +4436,8 @@ rs6000_option_override_internal (bool global_init_p)
if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
{
if (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11)
+ || rs6000_tune == PROCESSOR_POWER11
+ || rs6000_tune == PROCESSOR_FUTURE)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION;
else
rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION;
@@ -4462,6 +4468,7 @@ rs6000_option_override_internal (bool global_init_p)
&& rs6000_tune != PROCESSOR_POWER9
&& rs6000_tune != PROCESSOR_POWER10
&& rs6000_tune != PROCESSOR_POWER11
+ && rs6000_tune != PROCESSOR_FUTURE
&& rs6000_tune != PROCESSOR_PPCA2
&& rs6000_tune != PROCESSOR_CELL
&& rs6000_tune != PROCESSOR_PPC476);
@@ -4477,6 +4484,7 @@ rs6000_option_override_internal (bool global_init_p)
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
|| rs6000_tune == PROCESSOR_POWER11
+ || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_PPCE500MC
|| rs6000_tune == PROCESSOR_PPCE500MC64
|| rs6000_tune == PROCESSOR_PPCE5500
@@ -4777,6 +4785,7 @@ rs6000_option_override_internal (bool global_init_p)
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
+ case PROCESSOR_FUTURE:
rs6000_cost = &power10_cost;
break;
@@ -5950,6 +5959,8 @@ rs6000_machine_from_flags (void)
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
| OPTION_MASK_ALTIVEC);
+ if ((arch_flags & ARCH_MASK_FUTURE) != 0)
+ return "future";
if ((arch_flags & ARCH_MASK_POWER11) != 0)
return "power11";
if ((arch_flags & ARCH_MASK_POWER10) != 0)
@@ -10201,6 +10212,7 @@ rs6000_reassociation_width (unsigned int opc
ATTRIBUTE_UNUSED,
case PROCESSOR_POWER9:
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
+ case PROCESSOR_FUTURE:
if (DECIMAL_FLOAT_MODE_P (mode))
return 1;
if (VECTOR_MODE_P (mode))
@@ -18288,7 +18300,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
rtx_insn *dep_insn, int cost,
/* Separate a load from a narrower, dependent store. */
if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11)
+ || rs6000_tune == PROCESSOR_POWER11
+ || rs6000_tune == PROCESSOR_FUTURE)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (PATTERN (dep_insn)) == SET
&& MEM_P (XEXP (PATTERN (insn), 1))
@@ -18328,6 +18341,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
rtx_insn *dep_insn, int cost,
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
|| rs6000_tune == PROCESSOR_POWER11
+ || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_CELL)
&& recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0))
@@ -18903,6 +18917,7 @@ rs6000_issue_rate (void)
return 6;
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
+ case PROCESSOR_FUTURE:
return 8;
default:
return 1;
@@ -19618,10 +19633,11 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED,
int sched_verbose,
if (rs6000_tune == PROCESSOR_POWER6)
load_store_pendulum = 0;
- /* Do Power10/Power11 dependent reordering. */
+ /* Do Power10/Power11/future dependent reordering. */
if (last_scheduled_insn
&& (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11))
+ || rs6000_tune == PROCESSOR_POWER11
+ || rs6000_tune == PROCESSOR_FUTURE))
power10_sched_reorder (ready, n_ready - 1);
return rs6000_issue_rate ();
@@ -19645,10 +19661,11 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose,
rtx_insn **ready,
&& recog_memoized (last_scheduled_insn) >= 0)
return power9_sched_reorder2 (ready, *pn_ready - 1);
- /* Do Power10/Power11 dependent reordering. */
+ /* Do Power10/Power11/future dependent reordering. */
if (last_scheduled_insn
&& (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11))
+ || rs6000_tune == PROCESSOR_POWER11
+ || rs6000_tune == PROCESSOR_FUTURE))
return power10_sched_reorder (ready, *pn_ready - 1);
return cached_can_issue_more;
@@ -22866,7 +22883,8 @@ rs6000_register_move_cost (machine_mode mode,
out to be a nop. */
if (rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11)
+ || rs6000_tune == PROCESSOR_POWER11
+ || rs6000_tune == PROCESSOR_FUTURE)
ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
else
ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 14dc66676c1b..cbb2d0632981 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -531,6 +531,7 @@ extern int rs6000_vector_align[];
#define TARGET_POWER9 ((rs6000_arch_flags & ARCH_MASK_POWER9) != 0)
#define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
#define TARGET_POWER11 ((rs6000_arch_flags & ARCH_MASK_POWER11) != 0)
+#define TARGET_FUTURE ((rs6000_arch_flags & ARCH_MASK_FUTURE) != 0)
/* In the past we represented power8, power10 as an ISA bit and used internal
switches the user was not supposed to use for -mpower8-internal and
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0524cf8ee6f3..5722a67f9699 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -350,7 +350,7 @@
ppc750,ppc7400,ppc7450,
ppc403,ppc405,ppc440,ppc476,
ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
- power4,power5,power6,power7,power8,power9,power10,power11,
+ power4,power5,power6,power7,power8,power9,power10,power11,future,
rs64a,mpccore,cell,ppca2,titan"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
