https://gcc.gnu.org/g:d1a8b7b62c9e590b6eb9486fbfc207134a0994d0
commit d1a8b7b62c9e590b6eb9486fbfc207134a0994d0
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Jun 13 14:50:24 2024 -0400
Possibly restrict SPRs from holding small integers or CCs.
2024-06-13 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
support for -mccspr and -mintspr which controls whether SPRs can
hold
condition code modes or small integers.
(rs6000_debug_reg_global): Print out -mccspr and -mintspr options.
* config/rs6000/rs6000.opt (-mccspr): New option.
(-mintspr): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 35 +++++++++++++++++++++++++++++------
gcc/config/rs6000/rs6000.opt | 8 ++++++++
2 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 16c66c102031..43ecb432adef 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1940,16 +1940,33 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
return mode == Pmode || mode == SImode;
/* Do some consistancy checks for SPRs. Don't allow complex modes.
- VRSAVE/VSCR are always 32-bit SPRs. Don't allow floating point modes in
- the other SPRs. Don't allow large modes that don't fit in a single
- register. */
+
+ VRSAVE/VSCR are always 32-bit SPRs.
+
+ Don't allow floating point modes in the other SPRs. Don't allow large
+ modes that don't fit in a single register.
+
+ Optionally restrict integer modes to be size of pointers which means the
+ register allocator will not use the SPR to hold QImode, HImode, and maybe
+ SImode values instead of spilling them to the stack.
+
+ Optionally restrict SPRs not to hold condition codes. */
if (regno == VRSAVE_REGNO || regno == VSCR_REGNO)
return (!orig_complex_p && mode == SImode);
if (regno == LR_REGNO || regno == CTR_REGNO)
- return (!orig_complex_p
- && GET_MODE_SIZE (mode) <= UNITS_PER_WORD
- && !SCALAR_FLOAT_MODE_P (mode));
+ {
+ if (orig_complex_p || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+ return 0;
+
+ if (GET_MODE_CLASS (mode) == MODE_CC)
+ return TARGET_CCSPR != 0;
+
+ if (GET_MODE_CLASS (mode) == MODE_INT)
+ return (TARGET_INTSPR || mode == Pmode);
+
+ return 0;
+ }
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
@@ -2606,6 +2623,12 @@ rs6000_debug_reg_global (void)
if (TARGET_DIRECT_MOVE_128)
fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
(int)VECTOR_ELEMENT_MFVSRLD_64BIT);
+
+ fprintf (stderr, DEBUG_FMT_S, "Condition modes in SPRS",
+ TARGET_CCSPR ? "yes" : "no");
+
+ fprintf (stderr, DEBUG_FMT_S, "Small integer modes in SPRS",
+ TARGET_INTSPR ? "yes" : "no");
}
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 70fd7080bc52..7208070f54c6 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -630,6 +630,14 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
+mccspr
+Target Var(TARGET_CCSPR) Init(1)
+Generate (do not generate) code that allows SPRs to hold condition codes.
+
+mintspr
+Target Var(TARGET_INTSPR) Init(1)
+Generate (do not generate) code that allows SPRs to hold small integers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
