https://gcc.gnu.org/g:929c37f970cd75190f1b7af30c33e422c2a4952c
commit 929c37f970cd75190f1b7af30c33e422c2a4952c
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue May 28 17:36:48 2024 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.tar | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
index 3b2a674be1d..34207e707f6 100644
--- a/gcc/ChangeLog.tar
+++ b/gcc/ChangeLog.tar
@@ -1,3 +1,19 @@
+==================== Branch work167-tar, patch #206 ====================
+
+Add more SPR register debug options.
+
+2024-05-28 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add more
+ debug options for seeing what modes get stored in SPR registers.
+ * config/rs6000/rs6000.opt (-msispr): New SPR mode debut option.
+ (-mhispr): Likewise.
+ (-mqispr): Likewise.): Likewise.
+ (-msfspr): Likewise.
+ (-mdfspr): Likewise.
+
==================== Branch work167-tar, patch #205 ====================
Fix test for TAR register.
