[gcc(refs/users/meissner/heads/work167-tar)] Add more SPR register debug options.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:309a32739e2d075bd62bf6767295acef596fe16c

commit 309a32739e2d075bd62bf6767295acef596fe16c
Author: Michael Meissner <meiss...@linux.ibm.com>
Date:   Tue May 28 17:23:23 2024 -0400

    Add more SPR register debug options.
    
    2024-05-28  Michael Meissner  <meiss...@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add 
more
            debug options for seeing what modes get stored in SPR registers.
            * config/rs6000/rs6000.opt (-msispr): New SPR mode debut option.
            (-mhispr): Likewise.
            (-mqispr): Likewise.): Likewise.
            (-msfspr): Likewise.
            (-mdfspr): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc  | 30 +++++++++++++++++++++++-------
 gcc/config/rs6000/rs6000.opt | 20 ++++++++++++++++++++
 2 files changed, 43 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c6fb978977c..9a7b4cc1138 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1959,16 +1959,32 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
        if (GET_MODE_CLASS (mode) == MODE_CC)
          return TARGET_CCSPR != 0;
 
-       if (SCALAR_FLOAT_MODE_P (mode))
-         return TARGET_FPSPR != 0;
+       switch (mode)
+         {
+         case E_QImode:
+           return (TARGET_INTSPR || TARGET_QISPR);
 
-       if (!SCALAR_INT_MODE_P (mode))
-         return false;
+         case E_HImode:
+           return (TARGET_INTSPR || TARGET_HISPR);
 
-       if (TARGET_INTSPR)
-         return true;
+         case E_SImode:
+           return (TARGET_INTSPR || TARGET_SISPR || reg_size == 4);
+
+         case E_DImode:
+           return (reg_size == 8);
+
+         case E_SFmode:
+         case E_SDmode:
+           return (TARGET_FPSPR || TARGET_SFSPR);
 
-       return GET_MODE_SIZE (mode) == reg_size;
+         case E_DFmode:
+         case E_DDmode:
+           return (TARGET_FPSPR || TARGET_DFSPR);
+
+         default:
+           break;
+         }
+       return false;
       }
 
     default:
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 0384b92344f..7a0b52ab6e1 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -638,6 +638,18 @@ mintspr
 Target Undocumented Var(TARGET_INTSPR) Init(0) Save
 Allow (do not allow) small integers in SPR registers.
 
+msispr
+Target Undocumented Var(TARGET_SISPR) Init(0) Save
+Allow (do not allow) SImode in SPR registers.
+
+mhispr
+Target Undocumented Var(TARGET_HISPR) Init(0) Save
+Allow (do not allow) HImode in SPR registers.
+
+mqispr
+Target Undocumented Var(TARGET_QISPR) Init(0) Save
+Allow (do not allow) QImode in SPR registers.
+
 mccspr
 Target Undocumented Var(TARGET_CCSPR) Init(0) Save
 Allow (do not allow) condition codes in SPR registers.
@@ -646,6 +658,14 @@ mfpspr
 Target Undocumented Var(TARGET_FPSPR) Init(0) Save
 Allow (do not allow) floating point in SPR registers.
 
+msfspr
+Target Undocumented Var(TARGET_SFSPR) Init(0) Save
+Allow (do not allow) SFmode in SPR registers.
+
+mdfspr
+Target Undocumented Var(TARGET_DFSPR) Init(0) Save
+Allow (do not allow) DFmode in SPR registers.
+
 ; Documented parameters
 
 -param=rs6000-vect-unroll-limit=