https://gcc.gnu.org/g:d5fdd314b266f9830ab28db14db7d0aa3f59f424
commit d5fdd314b266f9830ab28db14db7d0aa3f59f424
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri May 24 23:15:34 2024 -0400
Add -mccspr and -mfpspr
2024-05-24 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
support for -mccspr and -mfpspr debug switches
* config/rs6000/rs6000.md (movcc_<mode>): Add spr support back in.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov<mode>_softfloat): Likewise.
(mov<mode>_softfloat32): Likewise.
(ov<mode>_hardfloat64): Likewise.
(mov<mode>_softfloat64): Likewise.
(indirect_jump<mode>): Add TAR register support.
(@indirect_jump<mode>_nospec): Likewise.
* config/rs6000/rs6000.opt (-mccspr): New switch.
(-mfpspr): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 31 ++++++++----
gcc/config/rs6000/rs6000.md | 118 ++++++++++++++++++++++++++-----------------
gcc/config/rs6000/rs6000.opt | 8 +++
3 files changed, 101 insertions(+), 56 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index fa330c2a4b1..c6fb978977c 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1943,20 +1943,33 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
SPR. */
switch (regno)
{
- /* 32-bit registers. */
case VRSAVE_REGNO:
case VSCR_REGNO:
- return (!orig_complex_p && mode == SImode);
-
- /* Registers that hold addresses. */
case LR_REGNO:
case CTR_REGNO:
case TAR_REGNO:
- return (!orig_complex_p
- && (mode == Pmode
- || (TARGET_INTSPR
- && SCALAR_INT_MODE_P (mode)
- && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)));
+ {
+ unsigned reg_size = ((regno == VRSAVE_REGNO || regno == VSCR_REGNO)
+ ? 4
+ : UNITS_PER_WORD);
+
+ if (orig_complex_p || GET_MODE_SIZE (mode) > reg_size)
+ return false;
+
+ if (GET_MODE_CLASS (mode) == MODE_CC)
+ return TARGET_CCSPR != 0;
+
+ if (SCALAR_FLOAT_MODE_P (mode))
+ return TARGET_FPSPR != 0;
+
+ if (!SCALAR_INT_MODE_P (mode))
+ return false;
+
+ if (TARGET_INTSPR)
+ return true;
+
+ return GET_MODE_SIZE (mode) == reg_size;
+ }
default:
break;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b5dc0719a88..28f8ebee738 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8120,9 +8120,9 @@
(define_insn "*movcc_<mode>"
[(set (match_operand:CC_any 0 "nonimmediate_operand"
- "=y,x,?y,y,r,r,r,r,r,m")
+ "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
(match_operand:CC_any 1 "general_operand"
- " y,r, r,O,x,y,r,I,m,r"))]
+ " y,r, r,O,x,y,r,I,*h, r,m,r"))]
"register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode)"
"@
@@ -8134,6 +8134,8 @@
mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
mr %0,%1
li %0,%1
+ mf%1 %0
+ mt%0 %1
lwz%U1%X1 %0,%1
stw%U0%X0 %1,%0"
[(set_attr_alternative "type"
@@ -8147,9 +8149,11 @@
(const_string "mfcrf") (const_string "mfcr"))
(const_string "integer")
(const_string "integer")
+ (const_string "mfjmpr")
+ (const_string "mtjmpr")
(const_string "load")
(const_string "store")])
- (set_attr "length" "*,*,12,*,*,8,*,*,*,*")])
+ (set_attr "length" "*,*,12,*,*,8,*,*,*,*,*,*")])
;; For floating-point, we normally deal with the floating-point registers
;; unless -msoft-float is used. The sole exception is that parameter passing
@@ -8200,17 +8204,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR XXSPLTIDP
+;; MR MT<x> MF<x> NOP XXSPLTIDP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, wa")
+ !r, *c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, eP"))]
+ r, r, *h, 0, eP"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -8230,29 +8234,32 @@
fmr %0,%1
xscpsgndp %x0,%x1,%x1
mr %0,%1
+ mt%0 %1
+ mf%1 %0
+ nop
#"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, vecperm")
+ *, mtjmpr, mfjmpr, *, vecperm")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, p10")
+ *, *, *, *, p10")
(set_attr "prefixed"
"*, *, *, *, *, *,
*, *, *, *, *, *,
- *, yes")])
+ *, *, *, *, yes")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
-;; FMR MR
+;; FMR MR MT%0 MF%1 NOP
(define_insn "movsd_hardfloat"
[(set (match_operand:SD 0 "nonimmediate_operand"
"=!r, d, m, ?Z, ?d, ?r,
- f, !r")
+ f, !r, *c*l, !r, *h")
(match_operand:SD 1 "input_operand"
"m, ?Z, r, wx, r, d,
- f, r"))]
+ f, r, r, *h, 0"))]
"(register_operand (operands[0], SDmode)
|| register_operand (operands[1], SDmode))
&& TARGET_HARD_FLOAT"
@@ -8264,43 +8271,49 @@
mtvsrwz %x0,%1
mfvsrwz %0,%x1
fmr %0,%1
- mr %0,%1"
+ mr %0,%1
+ mt%0 %1
+ mf%1 %0
+ nop"
[(set_attr "type"
"load, fpload, store, fpstore, mtvsr, mfvsr,
- fpsimple, *")
+ fpsimple, *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, p7, *, *, p8v, p8v,
- *, *")])
+ *, *, *, *, *")])
-;; MR LWZ STW LI
-;; LIS G-const. F/n-const
+;; MR MT%0 MF%0 LWZ STW LI
+;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
- "=r, r, m, r,
- r, r, r")
+ "=r, *c*l, r, r, m, r,
+ r, r, r, *h")
(match_operand:FMOVE32 1 "input_operand"
- "r, m, r, I,
- L, G, Fn"))]
+ "r, r, *h, m, r, I,
+ L, G, Fn, 0"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))
&& TARGET_SOFT_FLOAT"
"@
mr %0,%1
+ mt%0 %1
+ mf%1 %0
lwz%U1%X1 %0,%1
stw%U0%X0 %1,%0
li %0,%1
lis %0,%v1
#
- #"
+ #
+ nop"
[(set_attr "type"
- "*, load, store, *,
- *, *, *")
+ "*, mtjmpr, mfjmpr, load, store, *,
+ *, *, *, *")
(set_attr "length"
- "*, *, *, *,
- *, *, 8")])
+ "*, *, *, *, *, *,
+ *, *, 8, *")])
;; Like movsf, but adjust a SI value to be used in a SF context, i.e.
;; (set (reg:SF ...) (subreg:SF (reg:SI ...) 0))
@@ -8580,20 +8593,20 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
-;; STD LD MR
-;; MFVSRD MTVSRD XXSPLTIDP
+;; STD LD MR MT{CTR,LR} MF{CTR,LR}
+;; NOP MFVSRD MTVSRD XXSPLTIDP
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- YZ, r, !r,
- r, <f64_dm>, wa")
+ YZ, r, !r, *c*l, !r,
+ *h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, YZ, r,
- <f64_dm>, r, eP"))]
+ r, YZ, r, r, *h,
+ 0, <f64_dm>, r, eP"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8611,34 +8624,40 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
+ mt%0 %1
+ mf%1 %0
+ nop
mfvsrd %0,%x1
mtvsrd %x0,%1
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
- store, load, *,
- mfvsr, mtvsr, vecperm")
+ store, load, *, mtjmpr, mfjmpr,
+ *, mfvsr, mtvsr, vecperm")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *,
- p8v, p8v, p10")
+ *, *, *, *, *,
+ *, p8v, p8v, p10")
(set_attr "prefixed"
"*, *, *, *, *,
*, *, *, *, *,
- *, *, *,
- *, *, *")])
+ *, *, *, *, *,
+ *, *, *, *")])
-;; STD LD MR G-const H-const F-const
+;; STD LD MR MT<SPR> MF<SPR> G-const
+;; H-const F-const Special
(define_insn "*mov<mode>_softfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=Y, r, r, r, r, r")
+ "=Y, r, r, *c*l, r, r,
+ r, r, *h")
(match_operand:FMOVE64 1 "input_operand"
- "r, Y, r, G, H, F"))]
+ "r, Y, r, r, *h, G,
+ H, F, 0"))]
"TARGET_POWERPC64 && TARGET_SOFT_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
@@ -8647,14 +8666,19 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
+ mt%0 %1
+ mf%1 %0
#
#
- #"
+ #
+ nop"
[(set_attr "type"
- "store, load, *, *, *, *")
+ "store, load, *, mtjmpr, mfjmpr, *,
+ *, *, *")
(set_attr "length"
- "*, *, *, 8, 12, 16")])
+ "*, *, *, *, *, 8,
+ 12, 16, *")])
;; Split the VSX prefixed instruction to support SFmode and DFmode scalar
;; constants that look like DFmode floating point values where both elements
@@ -13474,14 +13498,14 @@
(define_insn "*indirect_jump<mode>"
[(set (pc)
- (match_operand:P 0 "register_operand" "c,*l"))]
+ (match_operand:P 0 "register_operand" "wt,c,*l"))]
"rs6000_speculate_indirect_jumps"
"b%T0"
[(set_attr "type" "jmpreg")])
(define_insn "@indirect_jump<mode>_nospec"
- [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))
- (clobber (match_operand:CC 1 "cc_reg_operand" "=y,y"))]
+ [(set (pc) (match_operand:P 0 "register_operand" "wt,c,*l"))
+ (clobber (match_operand:CC 1 "cc_reg_operand" "=y,y,y"))]
"!rs6000_speculate_indirect_jumps"
"crset %E1\;beq%T0- %1\;b $"
[(set_attr "type" "jmpreg")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index bac74695f64..0384b92344f 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -638,6 +638,14 @@ mintspr
Target Undocumented Var(TARGET_INTSPR) Init(0) Save
Allow (do not allow) small integers in SPR registers.
+mccspr
+Target Undocumented Var(TARGET_CCSPR) Init(0) Save
+Allow (do not allow) condition codes in SPR registers.
+
+mfpspr
+Target Undocumented Var(TARGET_FPSPR) Init(0) Save
+Allow (do not allow) floating point in SPR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
