https://gcc.gnu.org/g:2b03ff803c7f0e6c4f695a0969c966f30c2cf9db
commit 2b03ff803c7f0e6c4f695a0969c966f30c2cf9db
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Mon May 20 17:18:26 2024 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.tar | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 93 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
index 3e168fa367eb..c09b96a6afc1 100644
--- a/gcc/ChangeLog.tar
+++ b/gcc/ChangeLog.tar
@@ -1,6 +1,98 @@
+==================== Branch work166-tar, patch #202 ====================
+
+Add -mtar.
+
+gcc/
+
+2024-05-20 Michael Meissner <meiss...@linux.ibm.com>
+
+ * config/rs6000/constraints.md (h constraint): Add documentation for TAR
+ register.
+ (wt constraint): New constraint.
+ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mtar.
+ * config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register.
+ (alt_reg_names): Likewise.
+ (rs6000_hard_regno_mode_ok_uncached): Add support for -mintspr.
+ (rs6000_debug_reg_global): Print information about the TAR register and
+ the wt constraint.
+ (rs6000_init_hard_regno_mode_ok): Setup the TAR register. Set up the wt
+ constraint if -mtar.
+ (rs6000_option_override_internal): If -mtar, make sure we are running on
+ at least a power9.
+ (rs6000_conditional_register_usage): Enable TAR register if -mtar.
+ (print_operand): Handle the TAR register.
+ (rs6000_debugger_regno): Likewise.
+ (rs6000_opt_masks): Add -mtar.
+ * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register.
+ (FIXED_REGISTERS): Likewise.
+ (CALL_REALLY_USED_REGISTERS): Likewise.
+ (REG_ALLOC_ORDER): Likewise.
+ (enum reg_class): Add TAR_REGS register class.
+ (REG_CLASS_NAMES): Likewise.
+ (REG_CLASS_CONTENTS): Likewise.
+ (enum r6000_reg_class_enum): Add wt constraint.
+ (rs6000_reg_names): Add TAR register.
+ * config/rs6000/rs6000.md (TAR_REGNO): New constant.
+ (mov<mode>_internal): Add support for the TAR register.
+ (movcc_<mode>): Likewise.
+ (movsf_hardfloat): Likewise.
+ (movsf_hardfloat): Likewise.
+ (movsd_hardfloat): Likewise.
+ (mov<mode>_hardfloat64): Likewise.
+ (mov<mode>_softfloat64): Likewise.
+ (@tablejump<mode>_insn_normal): Likewise.
+ (@tablejump<mode>_insn_nospec): Likewise.
+ * config/rs6000/rs6000.opt (-mtar): New option.
+
+gcc/testsuite/
+
+2024-05-14 Michael Meissner <meiss...@linux.ibm.com>
+
+ * gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR register.
+ * gcc.target/powerpc/pr51513.c: Likewise.
+ * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
+
+==================== Branch work166-tar, patch #201 ====================
+
+Add -mmfspr
+
+2024-05-20 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mmfspr.
+ * config/rs6000/rs6000.cc (rs6000_register_move_cost): If -mmfspr, make
+ moves from CTR more expensive.
+ (rs6000_opt_masks): Add -mmfspr.
+ * config/rs6000/rs6000.opt (-mmfspr): New option.
+
+==================== Branch work166-tar, patch #200 ====================
+
+Add -mintspr
+
+2024-05-20 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mintspr.
+ * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict
+ modes that go in SPRs to modes that fit in the SPR and are not complex
+ modes. If -mintspr, restrict modes that go into SPRs to be scalar
+ integers.
+ (rs6000_opt_masks): Add -mintspr.
+ * config/rs6000/rs6000 (-mintspr): New option.
+
==================== Branch work166-tar, baseline ====================
+Add ChangeLog.tar and update REVISION.
+
+2024-05-02 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * ChangeLog.tar: New file for branch.
+ * REVISION: Update.
+
2024-05-17 Michael Meissner <meiss...@linux.ibm.com>
Clone branch
-
