https://gcc.gnu.org/g:5816726d26832b3d0f3a87f06b4b3e38982ce89c
commit 5816726d26832b3d0f3a87f06b4b3e38982ce89c
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Mon May 20 16:38:25 2024 -0400
Add -mmfspr
2024-05-20 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mmfspr.
* config/rs6000/rs6000.cc (rs6000_register_move_cost): If -mmfspr,
make
moves from CTR more expensive.
(rs6000_opt_masks): Add -mmfspr.
* config/rs6000/rs6000.opt (-mmfspr): New option.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000.cc | 12 ++++++++++++
gcc/config/rs6000/rs6000.opt | 4 ++++
3 files changed, 17 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 6fcbcbdadef7..47aca85aa4bc 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -136,6 +136,7 @@
| OPTION_MASK_INTSPR \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
+ | OPTION_MASK_MFSPR \
| OPTION_MASK_MMA \
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7d5b94cda101..ce1a49abe598 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -22807,6 +22807,17 @@ rs6000_register_move_cost (machine_mode mode,
ret = 2 * hard_regno_nregs (reg, mode);
}
+ /* Make moves from the CTR register more expensive so that the register
+ allocator does not think of these registers are useful for saving
+ results. */
+ else if (TARGET_MFSPR
+ && reg_classes_intersect_p (to, GENERAL_REGS)
+ && reg_classes_intersect_p (from, CTR_REGS))
+ {
+ rclass = from;
+ ret = 32;
+ }
+
/* Moves from/to GENERAL_REGS. */
else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
|| (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
@@ -24491,6 +24502,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "isel", OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
+ { "mfspr", OPTION_MASK_MFSPR, false, true },
{ "mma", OPTION_MASK_MMA, false, true },
{ "modulo", OPTION_MASK_MODULO, false, true },
{ "mulhw", OPTION_MASK_MULHW, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 2f3970b664cc..d45746bc24f4 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -634,6 +634,10 @@ mintspr
Target Undocumented Mask(INTSPR) Var(rs6000_isa_flags)
Disallow (allow) non-integer types in SPR registers.
+mmfspr
+Target Undocumented Mask(MFSPR) Var(rs6000_isa_flags)
+Disallow (allow) non-integer types in SPR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
