https://gcc.gnu.org/g:be9d1542324190545ef14f01c68cceabb085bdc0
commit be9d1542324190545ef14f01c68cceabb085bdc0
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue May 14 21:25:16 2024 -0400
Revert previous changes
Diff:
---
gcc/ChangeLog.tar | 101 +--------------------
gcc/config/rs6000/constraints.md | 5 +-
gcc/config/rs6000/rs6000-cpus.def | 13 +--
gcc/config/rs6000/rs6000.cc | 84 ++---------------
gcc/config/rs6000/rs6000.h | 31 +++----
gcc/config/rs6000/rs6000.md | 23 +++--
gcc/config/rs6000/rs6000.opt | 12 ---
gcc/doc/invoke.texi | 12 +--
gcc/lra-constraints.cc | 9 +-
gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c | 4 +-
gcc/testsuite/gcc.target/powerpc/pr51513.c | 4 +-
.../gcc.target/powerpc/safe-indirect-jump-3.c | 2 +-
12 files changed, 49 insertions(+), 251 deletions(-)
diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
index ad0c80ed7acc..5e1035a5f9f6 100644
--- a/gcc/ChangeLog.tar
+++ b/gcc/ChangeLog.tar
@@ -1,99 +1,8 @@
-==================== Branch work165-tar, patch #204 ====================
-
-Add -mintspr. Default -mtar for power10, not power9.
-
-2024-05-14 Michael Meissner <meiss...@linux.ibm.com>
-
- * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Don't set TAR
- options here.
- (OTHER_POWER10_MASKS): Set TAR options here. Add -mintspr.
- (POWERPC_MASKS): Add -mintspr.
- * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
- support for -mintspr.
- (rs6000_option_override_internal): Require -mcpu=power9 or -mcpu=power10
- to use -mtar.
- (rs6000_opt_masks): Add -mmfspr and -mintspr.
- * config/rs6000/rs6000.opt (-mintspr): New option.
-
-==================== Branch work165-tar, patch #203 ====================
-
-Limit SPR registers to hold only DImode/SImode.
-
-2024-05-08 Michael Meissner <meiss...@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Limit
- SPR registers to only hold SImode/DImode.
-
-==================== Branch work165-tar, patch #202 ====================
-
-Add -mfspr option.
-
-2024-05-08 Michael Meissner <meiss...@linux.ibm.com>
-
- * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mfspr
- support.
- (POWERPC_MASKS): Likewise.
- * config/rs6000/rs6000.cc (rs6000_register_move_cost): Likewise.
- * config/rs6000/rs6000.opt (-mfspr): Likewise.
-
-==================== Branch work165-tar, patch #201 ====================
-
-Fix tests if -mtar is used.
-
-2024-05-06 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/testsuite/
-
- * gcc.target/powerpc/ppc-switch-1.c: Add support for using the TAR
- register.
- * gcc.target/powerpc/pr51513.c: Likewise.
- * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
-
-==================== Branch work165-tar, patch #200 ====================
-
-Add support for -mtar
-
-2024-05-03 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/constraints.md (h constraint): Add tar register to
- documentation.
- (wt constraint): New constraint.
- * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mtar.
- (POWERPC_MASKS): Likewise.
- * config/rs6000/rs6000.cc (rs6000_reg_names): Add new tar register.
- (alt_reg_names): Likewise.
- (rs6000_debug_reg_global): Likewise.
- (rs6000_init_hard_regno_mode_ok): Likewise.
- (rs6000_option_override_internal): Likewise.
- (rs6000_conditional_register_usage): Likewise.
- (print_operand): Likewise.
- (rs6000_debugger_regno): Likewise.
- (rs6000_opt_masks): Likewise.
- * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Likewise.
- (FiXED_REGISTERS): Likewise.
- (CALL_REALLY_USED_REGISTERS): Likewise.
- (REG_ALLOC_ORDER): Likewise.
- (reg_class): Add new TAR_REGS register class.
- (REG_CLASS_NAMES): Likewise.
- (REG_CLASS_CONTENTS): Likewise.
- (r6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
- (REG_NAMES): Add tar register.
- * config/rs6000/rs6000.md (TAR_REGNO): New constant.
- (mov<mode>_internal): Add support for tar register.
- (movcc_<mode>): Likewise.
- (movsf_hardfloat): Likewise.
- (movsd_hardfloat): Likewise.
- (mov<mode>_softfloat): Likewise.
- (mov<mode>_hardfloat64): Likewise.
- (mov<mode>_softfloat64): Likewise.
- (@tablejump<mode>_insn_normal); Likewise.
- (@tablejump<mode>_insn_nospec); Likewise.
- * config/rs6000/rs6000.opt (-mtar): New option.
- * doc/invoke.texi (RS/6000 options): Document -mtar.
- * lra-constraints.md (lra_constraints): Print out insn that we can't
- generate reloads for.
+==================== Branch work165-tar, patch #204 was reverted
====================
+==================== Branch work165-tar, patch #203 was reverted
====================
+==================== Branch work165-tar, patch #202 was reverted
====================
+==================== Branch work165-tar, patch #201 was reverted
====================
+==================== Branch work165-tar, patch #200 was reverted
====================
==================== Branch work165-tar, baseline ====================
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 14f0465d7ae5..369a7b75042d 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
"@internal A compatibility alias for @code{wa}.")
(define_register_constraint "h" "SPECIAL_REGS"
- "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or
@code{tar}).")
+ "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
(define_register_constraint "c" "CTR_REGS"
"The count register, @code{ctr}.")
@@ -91,9 +91,6 @@
"@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
-(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
- "The tar register, @code{tar}.")
-
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 46e26b0df5ec..d625dbeb91fd 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -59,12 +59,9 @@
| OPTION_MASK_P8_FUSION_SIGN)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
- FLOAT128_HW here until we are ready to make -mfloat128 on by default. While
- ISA 2.07 (power9) supports the TAR register, don't enable it here, because
- it doesn't seem to help. */
+ FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
| OPTION_MASK_ISEL \
- | OPTION_MASK_MFSPR \
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
@@ -81,12 +78,9 @@
/* We comment out PCREL_OPT here to disable it by default because SPEC2017
performance was degraded by it. */
#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \
- | OPTION_MASK_INTSPR \
- | OPTION_MASK_MFSPR \
| OPTION_MASK_PCREL \
/* | OPTION_MASK_PCREL_OPT */ \
- | OPTION_MASK_PREFIXED \
- | OPTION_MASK_TAR)
+ | OPTION_MASK_PREFIXED)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
| OPTION_MASK_POWER10 \
@@ -139,10 +133,8 @@
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
- | OPTION_MASK_INTSPR \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
- | OPTION_MASK_MFSPR \
| OPTION_MASK_MMA \
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
@@ -166,7 +158,6 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
- | OPTION_MASK_TAR \
| OPTION_MASK_VSX)
#endif
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7f4ee65c42c4..5bb66dca81dc 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1224,8 +1224,8 @@ char rs6000_reg_names[][8] =
"lr", "ctr", "ca", "ap",
/* cr0..cr7 */
"0", "1", "2", "3", "4", "5", "6", "7",
- /* vrsave vscr sfp, tar */
- "vrsave", "vscr", "sfp", "tar",
+ /* vrsave vscr sfp */
+ "vrsave", "vscr", "sfp",
};
#ifdef TARGET_REGNAMES
@@ -1250,8 +1250,8 @@ static const char alt_reg_names[][8] =
"lr", "ctr", "ca", "ap",
/* cr0..cr7 */
"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
- /* vrsave vscr sfp, tar */
- "vrsave", "vscr", "sfp", "tar"
+ /* vrsave vscr sfp */
+ "vrsave", "vscr", "sfp",
};
#endif
@@ -1848,7 +1848,6 @@ static int
rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
- machine_mode orig_mode = mode;
if (COMPLEX_MODE_P (mode))
mode = GET_MODE_INNER (mode);
@@ -1930,23 +1929,8 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (CR_REGNO_P (regno))
return GET_MODE_CLASS (mode) == MODE_CC;
- /* If desired, limit SPR registers to integer modes that can fit in a single
- register. Do not allow complex modes. */
- switch (regno)
- {
- case LR_REGNO:
- case CTR_REGNO:
- case TAR_REGNO:
- case VRSAVE_REGNO:
- case VSCR_REGNO:
- case CA_REGNO:
- return (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (Pmode)
- && !COMPLEX_MODE_P (orig_mode)
- && (!TARGET_INTSPR || SCALAR_INT_MODE_P (mode)));
-
- default:
- break;
- }
+ if (CA_REGNO_P (regno))
+ return mode == Pmode || mode == SImode;
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
@@ -2320,7 +2304,6 @@ rs6000_debug_reg_global (void)
"vs");
rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
- rs6000_debug_reg_print (TAR_REGNO, TAR_REGNO, "tar");
rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
@@ -2337,7 +2320,6 @@ rs6000_debug_reg_global (void)
"wa reg_class = %s\n"
"we reg_class = %s\n"
"wr reg_class = %s\n"
- "wt reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
"\n",
@@ -2346,7 +2328,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
@@ -2797,7 +2778,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
- rs6000_regno_regclass[TAR_REGNO] = TAR_REGS;
rs6000_regno_regclass[CA_REGNO] = NO_REGS;
rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
@@ -2817,7 +2797,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
- reg_class_to_reg_type[(int)TAR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
@@ -3007,10 +2986,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE_128)
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
- /* Power9 adds a TAR register that can hold the target of a jump. */
- if (TARGET_TAR)
- rs6000_constraints[RS6000_CONSTRAINT_wt] = TAR_REGS;
-
/* Set up the reload helper and direct move functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
{
@@ -4218,15 +4193,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
}
- /* If -mtar, make sure we have at least a power9. */
- if (TARGET_TAR && !TARGET_P9_MISC)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_TAR) != 0)
- error ("%qs requires %qs", "-mtar", "-mcpu=power9");
-
- rs6000_isa_flags &= ~OPTION_MASK_TAR;
- }
-
/* Enable -mprefixed by default on power10 systems. */
if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_PREFIXED) ==
0)
rs6000_isa_flags |= OPTION_MASK_PREFIXED;
@@ -4370,15 +4336,6 @@ rs6000_option_override_internal (bool global_init_p)
SUB3TARGET_OVERRIDE_OPTIONS;
#endif
- /* TAR register was introduced in power9. */
- if (TARGET_TAR && !TARGET_P9_MISC)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_TAR) != 0)
- error ("%qs requires at least %qs", "-mtar", "-mcpu=power9");
-
- rs6000_isa_flags &= ~OPTION_MASK_TAR;
- }
-
/* If the ABI has support for PC-relative relocations, enable it by default.
This test depends on the sub-target tests above setting the code model to
medium for ELF v2 systems. */
@@ -10250,9 +10207,6 @@ rs6000_conditional_register_usage (void)
for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
fixed_regs[i] = call_used_regs[i] = 1;
}
-
- if (TARGET_TAR)
- fixed_regs[TAR_REGNO] = 0;
}
@@ -14401,13 +14355,10 @@ print_operand (FILE *file, rtx x, int code)
if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
x = XVECEXP (x, 0, 0);
if (!REG_P (x) || (REGNO (x) != LR_REGNO
- && REGNO (x) != CTR_REGNO
- && REGNO (x) != TAR_REGNO))
+ && REGNO (x) != CTR_REGNO))
output_operand_lossage ("invalid %%T value");
else if (REGNO (x) == LR_REGNO)
fputs ("lr", file);
- else if (REGNO (x) == TAR_REGNO)
- fputs ("tar", file);
else
fputs ("ctr", file);
return;
@@ -22829,18 +22780,6 @@ rs6000_register_move_cost (machine_mode mode,
ret = 2 * hard_regno_nregs (reg, mode);
}
- /* Make moves from the CTR/TAR registers more expensive so that the register
- allocator does not think of these registers are useful for saving
- results. */
- else if (TARGET_MFSPR
- && reg_classes_intersect_p (to, GENERAL_REGS)
- && (reg_classes_intersect_p (from, CTR_REGS)
- || reg_classes_intersect_p (from, TAR_REGS)))
- {
- rclass = from;
- ret = 32;
- }
-
/* Moves from/to GENERAL_REGS. */
else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
|| (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
@@ -24245,8 +24184,6 @@ rs6000_debugger_regno (unsigned int regno, unsigned int
format)
return 108;
if (regno == CTR_REGNO)
return 109;
- if (regno == TAR_REGNO)
- return 111;
if (regno == CA_REGNO)
return 101; /* XER */
/* Special handling for CR for .debug_frame: rs6000_emit_prologue has
@@ -24264,7 +24201,7 @@ rs6000_debugger_regno (unsigned int regno, unsigned int
format)
/* These do not make much sense. */
if (regno == FRAME_POINTER_REGNUM)
- return FIRST_PSEUDO_REGISTER;
+ return 111;
if (regno == ARG_POINTER_REGNUM)
return 67;
if (regno == 64)
@@ -24287,8 +24224,6 @@ rs6000_debugger_regno (unsigned int regno, unsigned int
format)
return 65;
if (regno == CTR_REGNO)
return 66;
- if (regno == TAR_REGNO)
- return 111;
if (regno == CA_REGNO)
return 76; /* XER */
if (CR_REGNO_P (regno))
@@ -24525,11 +24460,9 @@ static struct rs6000_opt_mask const rs6000_opt_masks[]
=
{ "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
{ "htm", OPTION_MASK_HTM, false, true },
- { "intspr", OPTION_MASK_INTSPR, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
- { "mfspr", OPTION_MASK_MFSPR, false, true },
{ "mma", OPTION_MASK_MMA, false, true },
{ "modulo", OPTION_MASK_MODULO, false, true },
{ "mulhw", OPTION_MASK_MULHW, false, true },
@@ -24553,7 +24486,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
{ "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
{ "string", 0, false, true },
- { "tar", OPTION_MASK_TAR, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
#ifdef OPTION_MASK_64BIT
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ae9aff951956..2e60a0395adc 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -788,7 +788,7 @@ enum data_align { align_abi, align_opt, align_both };
Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
pointer, which is eventually eliminated in favor of SP or FP. */
-#define FIRST_PSEUDO_REGISTER 112
+#define FIRST_PSEUDO_REGISTER 111
/* Use standard DWARF numbering for DWARF debugging information. */
#define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0)
@@ -824,8 +824,8 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 1, 1, \
/* cr0..cr7 */ \
0, 0, 0, 0, 0, 0, 0, 0, \
- /* vrsave vscr sfp, tar */ \
- 1, 1, 1, 1 \
+ /* vrsave vscr sfp */ \
+ 1, 1, 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -848,8 +848,8 @@ enum data_align { align_abi, align_opt, align_both };
1, 1, 1, 1, \
/* cr0..cr7 */ \
1, 1, 0, 0, 0, 1, 1, 1, \
- /* vrsave vscr sfp, tar */ \
- 0, 0, 0, 1 \
+ /* vrsave vscr sfp */ \
+ 0, 0, 0 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -878,7 +878,6 @@ enum data_align { align_abi, align_opt, align_both };
r0 (not saved; cannot be base reg)
r31 - r13 (saved; order given to save least number)
r12 (not saved; if used for DImode or DFmode would use r13)
- tar (not saved; tar is preferred over ctr or lr)
ctr (not saved; when we have the choice ctr is better)
lr (saved)
r1, r2, ap, ca (fixed)
@@ -921,7 +920,7 @@ enum data_align { align_abi, align_opt, align_both };
3, EARLY_R12 11, 0, \
31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
18, 17, 16, 15, 14, 13, LATE_R12 \
- 111, 97, 96, \
+ 97, 96, \
1, MAYBE_R2_FIXED 99, 98, \
/* AltiVec registers. */ \
64, 65, \
@@ -1096,7 +1095,6 @@ enum reg_class
GEN_OR_VSX_REGS,
LINK_REGS,
CTR_REGS,
- TAR_REGS,
LINK_OR_CTR_REGS,
SPECIAL_REGS,
SPEC_OR_GEN_REGS,
@@ -1126,7 +1124,6 @@ enum reg_class
"GEN_OR_VSX_REGS", \
"LINK_REGS", \
"CTR_REGS", \
- "TAR_REGS", \
"LINK_OR_CTR_REGS", \
"SPECIAL_REGS", \
"SPEC_OR_GEN_REGS", \
@@ -1167,24 +1164,22 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \
/* CTR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \
- /* TAR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, \
/* LINK_OR_CTR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00008003 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \
/* SPECIAL_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00009003 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \
/* SPEC_OR_GEN_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000000, 0x0000d00b }, \
+ { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \
/* CR0_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \
/* CR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \
/* NON_FLOAT_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000000, 0x0000cffb }, \
+ { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \
/* CA_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \
/* ALL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0xffffffff, 0x0000ffff } \
+ { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \
}
/* The same information, inverted:
@@ -1206,7 +1201,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wa, /* Any VSX register */
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
- RS6000_CONSTRAINT_wt, /* TAR register. */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
RS6000_CONSTRAINT_MAX
@@ -2085,8 +2079,7 @@ extern char rs6000_reg_names[][8]; /* register
names (0 vs. %r0). */
&rs6000_reg_names[108][0], /* vrsave */ \
&rs6000_reg_names[109][0], /* vscr */ \
\
- &rs6000_reg_names[110][0], /* sfp */ \
- &rs6000_reg_names[111][0] /* tar */ \
+ &rs6000_reg_names[110][0] /* sfp */ \
}
/* Table of additional register names to use in user input. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5897da7d38de..41a5b86d3c63 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -51,7 +51,6 @@
(VRSAVE_REGNO 108)
(VSCR_REGNO 109)
(FRAME_POINTER_REGNUM 110)
- (TAR_REGNO 111)
])
;;
@@ -8073,7 +8072,7 @@
[(set (match_operand:QHI 0 "nonimmediate_operand"
"=r, r, wa, m, ?Z, r,
wa, wa, wa, v, ?v, r,
- wa, r, *wt*c*l, *h")
+ wa, r, *c*l, *h")
(match_operand:QHI 1 "input_operand"
"r, m, ?Z, r, wa, i,
wa, O, wM, wB, wS, wa,
@@ -8124,9 +8123,9 @@
(define_insn "*movcc_<mode>"
[(set (match_operand:CC_any 0 "nonimmediate_operand"
- "=y,x,?y,y,r,r,r,r, r,*wt*c*l,r,m")
+ "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
(match_operand:CC_any 1 "general_operand"
- " y,r, r,O,x,y,r,I,*h, r,m,r"))]
+ " y,r, r,O,x,y,r,I,*h, r,m,r"))]
"register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode)"
"@
@@ -8214,7 +8213,7 @@
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *wt*c*l, !r, *h, wa")
+ !r, *c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
@@ -8260,7 +8259,7 @@
(define_insn "movsd_hardfloat"
[(set (match_operand:SD 0 "nonimmediate_operand"
"=!r, d, m, ?Z, ?d, ?r,
- f, !r, *wt*c*l, !r, *h")
+ f, !r, *c*l, !r, *h")
(match_operand:SD 1 "input_operand"
"m, ?Z, r, wx, r, d,
f, r, r, *h, 0"))]
@@ -8290,7 +8289,7 @@
;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
- "=r, *wt*c*l, r, r, m, r,
+ "=r, *c*l, r, r, m, r,
r, r, r, *h")
(match_operand:FMOVE32 1 "input_operand"
@@ -8604,7 +8603,7 @@
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- YZ, r, !r, *wt*c*l, !r,
+ YZ, r, !r, *c*l, !r,
*h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
@@ -8656,7 +8655,7 @@
(define_insn "*mov<mode>_softfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=Y, r, r, *wt*c*l,r, r,
+ "=Y, r, r, *c*l, r, r,
r, r, *h")
(match_operand:FMOVE64 1 "input_operand"
@@ -13618,7 +13617,7 @@
(define_insn "@tablejump<mode>_insn_normal"
[(set (pc)
- (match_operand:P 0 "register_operand" "wt,c,*l"))
+ (match_operand:P 0 "register_operand" "c,*l"))
(use (label_ref (match_operand 1)))]
"rs6000_speculate_indirect_jumps"
"b%T0"
@@ -13626,9 +13625,9 @@
(define_insn "@tablejump<mode>_insn_nospec"
[(set (pc)
- (match_operand:P 0 "register_operand" "wt,c,*l"))
+ (match_operand:P 0 "register_operand" "c,*l"))
(use (label_ref (match_operand 1)))
- (clobber (match_operand:CC 2 "cc_reg_operand" "=y,y,y"))]
+ (clobber (match_operand:CC 2 "cc_reg_operand" "=y,y"))]
"!rs6000_speculate_indirect_jumps"
"crset %E2\;beq%T0- %2\;b $"
[(set_attr "type" "jmpreg")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 9e9efa60bea5..70fd7080bc52 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -607,18 +607,6 @@ mmma
Target Mask(MMA) Var(rs6000_isa_flags)
Generate (do not generate) MMA instructions.
-mtar
-Target Mask(TAR) Var(rs6000_isa_flags)
-Generate (do not generate) code using the TAR register.
-
-mmfspr
-Target Undocumented Mask(MFSPR) Var(rs6000_isa_flags)
-Generate (do not generate) code making move from SPR register expensive.
-
-mintspr
-Target Undocumented Mask(INTSPR) Var(rs6000_isa_flags)
-Require (disallow) SPR registers to hold only integer modes and not floating
point modes.
-
mrelative-jumptables
Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c0903d67615a..64e47803d2fd 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1332,7 +1332,7 @@ See RS/6000 and PowerPC Options.
-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg}
-mstack-protector-guard-offset=@var{offset} -mprefixed -mno-prefixed
-mpcrel -mno-pcrel -mmma -mno-mmma -mrop-protect -mno-rop-protect
--mprivileged -mno-privileged -mtar -mno-tar}
+-mprivileged -mno-privileged}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu
@@ -31351,7 +31351,7 @@ following options:
-mcrypto -mhtm -mpower8-fusion
-mquad-memory -mquad-memory-atomic -mfloat128
-mfloat128-hardware -mprefixed -mpcrel -mmma
--mrop-protect -mtar}
+-mrop-protect}
The particular options set for any particular CPU varies between
compiler versions, depending on what setting seems to produce optimal
@@ -32354,14 +32354,6 @@ Generate (do not generate) ROP protection instructions
when the target
processor supports them. Currently this option disables the shrink-wrap
optimization (@option{-fshrink-wrap}).
-@opindex mtar
-@opindex mno-tar
-@item -mtar
-@itemx -mno-tar
-Generate (do not generate) code that uses the @code{TAR} register.
-The @option{-mtar} option requires that the option
-@option{-mcpu=power9} (or later) is enabled.
-
@opindex mprivileged
@opindex mno-privileged
@item -mprivileged
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 4e72aa2d0782..10e3d4e40977 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -5346,12 +5346,9 @@ lra_constraints (bool first_p)
continue;
}
if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
- {
- debug_rtx (curr_insn);
- internal_error
- ("maximum number of generated reload insns per insn achieved (%d)",
- MAX_RELOAD_INSNS_NUMBER);
- }
+ internal_error
+ ("maximum number of generated reload insns per insn achieved (%d)",
+ MAX_RELOAD_INSNS_NUMBER);
new_insns_num++;
if (DEBUG_INSN_P (curr_insn))
{
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c
b/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c
index 7c1031d1b396..eb379a0f67d4 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c
@@ -1,8 +1,8 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 --param case-values-threshold=2" } */
-/* { dg-final { scan-assembler "mt\(ctr\|tar\)" } } */
-/* { dg-final { scan-assembler "b\(ctr\|tar\)" } } */
+/* { dg-final { scan-assembler "mtctr" } } */
+/* { dg-final { scan-assembler "bctr" } } */
/* Force using a dispatch table even though by default we would generate
ifs. */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr51513.c
b/gcc/testsuite/gcc.target/powerpc/pr51513.c
index 43c06da8f320..1c72a75502a1 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr51513.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr51513.c
@@ -1,8 +1,8 @@
/* { dg-do compile { target { powerpc*-*-linux* } } } */
/* { dg-options "-O2 -fjump-tables --param case-values-threshold=1" } */
/* Verify we created a jump table. */
-/* { dg-final { scan-assembler-times "mt\(ctr\|tar\) " 1 } } */
-/* { dg-final { scan-assembler-times "b\(ctr\|tar\)" 1 } } */
+/* { dg-final { scan-assembler-times "mtctr " 1 } } */
+/* { dg-final { scan-assembler-times "bctr" 1 } } */
/* Verify we eliminated the range check. */
/* { dg-final { scan-assembler-not "cmpldi" } } */
/* { dg-final { scan-assembler-not "cmplwi" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
index f61a4dbfad83..87881fb18fc5 100644
--- a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-3.c
@@ -47,5 +47,5 @@ int foo (int x)
}
/* { dg-final { scan-assembler "crset" } } */
-/* { dg-final { scan-assembler "beq\(ctr\|tar\)-" } } */
+/* { dg-final { scan-assembler "beqctr-" } } */
/* { dg-final { scan-assembler {b \$} } } */
