https://gcc.gnu.org/g:84becba734412efd2da9a75c859d2d776ab25666
commit 84becba734412efd2da9a75c859d2d776ab25666
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue May 14 13:44:45 2024 -0400
Add -mintspr. Default -mtar for power10, not power9.
2024-05-14 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Don't set
TAR
options here.
(OTHER_POWER10_MASKS): Set TAR options here. Add -mintspr.
(POWERPC_MASKS): Add -mintspr.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
support for -mintspr.
(rs6000_option_override_internal): Require -mcpu=power9 or
-mcpu=power10
to use -mtar.
(rs6000_opt_masks): Add -mmfspr and -mintspr.
* config/rs6000/rs6000.opt (-mintspr): New option.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 15 ++++++++++-----
gcc/config/rs6000/rs6000.cc | 19 ++++++++++++++++---
gcc/config/rs6000/rs6000.opt | 4 ++++
3 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index f53bd3e7dcba..46e26b0df5ec 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -51,19 +51,20 @@
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
- | OPTION_MASK_MFSPR \
| OPTION_MASK_QUAD_MEMORY \
- | OPTION_MASK_QUAD_MEMORY_ATOMIC \
- | OPTION_MASK_TAR)
+ | OPTION_MASK_QUAD_MEMORY_ATOMIC)
/* ISA masks setting fusion options. */
#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_FUSION_SIGN)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
- FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
+ FLOAT128_HW here until we are ready to make -mfloat128 on by default. While
+ ISA 2.07 (power9) supports the TAR register, don't enable it here, because
+ it doesn't seem to help. */
#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
| OPTION_MASK_ISEL \
+ | OPTION_MASK_MFSPR \
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
@@ -80,9 +81,12 @@
/* We comment out PCREL_OPT here to disable it by default because SPEC2017
performance was degraded by it. */
#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \
+ | OPTION_MASK_INTSPR \
+ | OPTION_MASK_MFSPR \
| OPTION_MASK_PCREL \
/* | OPTION_MASK_PCREL_OPT */ \
- | OPTION_MASK_PREFIXED)
+ | OPTION_MASK_PREFIXED \
+ | OPTION_MASK_TAR)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
| OPTION_MASK_POWER10 \
@@ -135,6 +139,7 @@
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
+ | OPTION_MASK_INTSPR \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MFSPR \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6bfcfdfb22c5..7f4ee65c42c4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1930,8 +1930,8 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (CR_REGNO_P (regno))
return GET_MODE_CLASS (mode) == MODE_CC;
- /* Limit SPR registers to integer modes that can fit in a single register.
- Do not allow complex modes or modes that need sign/zero extension. */
+ /* If desired, limit SPR registers to integer modes that can fit in a single
+ register. Do not allow complex modes. */
switch (regno)
{
case LR_REGNO:
@@ -1940,7 +1940,9 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
case VRSAVE_REGNO:
case VSCR_REGNO:
case CA_REGNO:
- return (orig_mode == Pmode || orig_mode == SImode);
+ return (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (Pmode)
+ && !COMPLEX_MODE_P (orig_mode)
+ && (!TARGET_INTSPR || SCALAR_INT_MODE_P (mode)));
default:
break;
@@ -4216,6 +4218,15 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
}
+ /* If -mtar, make sure we have at least a power9. */
+ if (TARGET_TAR && !TARGET_P9_MISC)
+ {
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_TAR) != 0)
+ error ("%qs requires %qs", "-mtar", "-mcpu=power9");
+
+ rs6000_isa_flags &= ~OPTION_MASK_TAR;
+ }
+
/* Enable -mprefixed by default on power10 systems. */
if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_PREFIXED) ==
0)
rs6000_isa_flags |= OPTION_MASK_PREFIXED;
@@ -24514,9 +24525,11 @@ static struct rs6000_opt_mask const rs6000_opt_masks[]
=
{ "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
{ "htm", OPTION_MASK_HTM, false, true },
+ { "intspr", OPTION_MASK_INTSPR, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
+ { "mfspr", OPTION_MASK_MFSPR, false, true },
{ "mma", OPTION_MASK_MMA, false, true },
{ "modulo", OPTION_MASK_MODULO, false, true },
{ "mulhw", OPTION_MASK_MULHW, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 8b21865f9831..9e9efa60bea5 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -615,6 +615,10 @@ mmfspr
Target Undocumented Mask(MFSPR) Var(rs6000_isa_flags)
Generate (do not generate) code making move from SPR register expensive.
+mintspr
+Target Undocumented Mask(INTSPR) Var(rs6000_isa_flags)
+Require (disallow) SPR registers to hold only integer modes and not floating
point modes.
+
mrelative-jumptables
Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
