https://gcc.gnu.org/g:dd388198b8be52ab378c935fc517a269e0ba741c
commit r15-323-gdd388198b8be52ab378c935fc517a269e0ba741c
Author: Christoph Müllner <christoph.muell...@vrull.eu>
Date: Tue May 7 22:59:44 2024 +0200
RISC-V: Add test for sraiw-31 special case
We already optimize a sign-extension of a right-shift by 31 in
<optab>si3_extend. Let's add a test for that (similar to
zero-extend-1.c).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sign-extend-1.c: New test.
Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
Diff:
---
gcc/testsuite/gcc.target/riscv/sign-extend-1.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
new file mode 100644
index 000000000000..e9056ec0d424
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+signed long
+foo1 (int i)
+{
+ return i >> 31;
+}
+/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],31" } } */
+
+/* { dg-final { scan-assembler-not "srai\t" } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "srliw\t" } } */
