https://gcc.gnu.org/g:3c0f768586bc719c0b78b49d676aaae1babfa872
commit 3c0f768586bc719c0b78b49d676aaae1babfa872
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed May 8 02:15:10 2024 -0400
Add -mfspr option.
2024-05-08 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mfspr
support.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_register_move_cost): Likewise.
* config/rs6000/rs6000.opt (-mfspr): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 2 ++
gcc/config/rs6000/rs6000.cc | 12 ++++++++++++
gcc/config/rs6000/rs6000.opt | 4 ++++
3 files changed, 18 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 29a5398b16d8..f53bd3e7dcba 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -51,6 +51,7 @@
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
+ | OPTION_MASK_MFSPR \
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
| OPTION_MASK_TAR)
@@ -136,6 +137,7 @@
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
+ | OPTION_MASK_MFSPR \
| OPTION_MASK_MMA \
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 463d27fa61ba..bfc207fb5f55 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -22804,6 +22804,18 @@ rs6000_register_move_cost (machine_mode mode,
ret = 2 * hard_regno_nregs (reg, mode);
}
+ /* Make moves from the CTR/TAR registers more expensive so that the register
+ allocator does not think of these registers are useful for saving
+ results. */
+ else if (TARGET_MFSPR
+ && reg_classes_intersect_p (to, GENERAL_REGS)
+ && (reg_classes_intersect_p (from, CTR_REGS)
+ || reg_classes_intersect_p (from, TAR_REGS)))
+ {
+ rclass = from;
+ ret = 32;
+ }
+
/* Moves from/to GENERAL_REGS. */
else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
|| (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 6e3fd1d07676..8b21865f9831 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -611,6 +611,10 @@ mtar
Target Mask(TAR) Var(rs6000_isa_flags)
Generate (do not generate) code using the TAR register.
+mmfspr
+Target Undocumented Mask(MFSPR) Var(rs6000_isa_flags)
+Generate (do not generate) code making move from SPR register expensive.
+
mrelative-jumptables
Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
