[gcc r15-226] pru: Implement zero fill for 64-bit registers

[Dimitar Dimitrov via Gcc-cvs]

https://gcc.gnu.org/g:ca7d6d729183685279a0d9dcd39aed11021f1dfa

commit r15-226-gca7d6d729183685279a0d9dcd39aed11021f1dfa
Author: Dimitar Dimitrov <dimi...@dinux.eu>
Date:   Sat Nov 18 23:05:09 2023 +0200

    pru: Implement zero fill for 64-bit registers
    
    Loading a constant zero in a 64-bit register now takes one instead of
    two instructions.
    
    gcc/ChangeLog:
    
            * config/pru/pru.md: New pattern alternative for zero-filling
            64-bit registers.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/pru/mov-0.c: New test.
    
    Signed-off-by: Dimitar Dimitrov <dimi...@dinux.eu>

Diff:
---
 gcc/config/pru/pru.md                | 18 ++++++++++--------
 gcc/testsuite/gcc.target/pru/mov-0.c | 19 +++++++++++++++++++
 2 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 8393d8f9607..0123952aa9e 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -248,8 +248,8 @@
 ; Forcing DI reg alignment (akin to microblaze's HARD_REGNO_MODE_OK)
 ; does not seem efficient, and will violate TI ABI.
 (define_insn "mov<mode>"
-  [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r,r")
-       (match_operand:MOV64 1 "general_operand"      "r,m,Um,r,T,J,nF"))]
+  [(set (match_operand:MOV64 0 "nonimmediate_operand" "=m,r,r,r,r,r,r,r")
+       (match_operand:MOV64 1 "general_operand"      "r,m,Z,Um,r,T,J,nF"))]
   ""
 {
   switch (which_alternative)
@@ -259,8 +259,10 @@
     case 1:
       return "lb%B1o\\t%b0, %1, %S1";
     case 2:
-      return "fill\\t%F0, 8";
+      return "zero\\t%F0, 8";
     case 3:
+      return "fill\\t%F0, 8";
+    case 4:
       /* careful with overlapping source and destination regs.  */
       gcc_assert (GP_REG_P (REGNO (operands[0])));
       gcc_assert (GP_REG_P (REGNO (operands[1])));
@@ -268,18 +270,18 @@
        return "mov\\t%N0, %N1\;mov\\t%F0, %F1";
       else
        return "mov\\t%F0, %F1\;mov\\t%N0, %N1";
-    case 4:
-      return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
     case 5:
-      return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+      return "ldi\\t%F0, %%pmem(%1)\;ldi\\t%N0, 0";
     case 6:
+      return "ldi\\t%F0, %1\;ldi\\t%N0, 0";
+    case 7:
       return "ldi32\\t%F0, %w1\;ldi32\\t%N0, %W1";
     default:
       gcc_unreachable ();
   }
 }
-  [(set_attr "type" "st,ld,alu,alu,alu,alu,alu")
-   (set_attr "length" "4,4,4,8,8,8,16")])
+  [(set_attr "type" "st,ld,alu,alu,alu,alu,alu,alu")
+   (set_attr "length" "4,4,4,4,8,8,8,16")])
 
 ;
 ; load_multiple pattern(s).
diff --git a/gcc/testsuite/gcc.target/pru/mov-0.c 
b/gcc/testsuite/gcc.target/pru/mov-0.c
new file mode 100644
index 00000000000..0190be36fa4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/mov-0.c
@@ -0,0 +1,19 @@
+/* Loading a register with constant 0 integer value.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int
+test_set_0_si (void)
+{
+  /* Since zero-extension is free, "zero" fill is not implemented for SI.  */
+  /* { dg-final { scan-assembler "ldi\\tr14(.b0)?, 0" } } */
+  return 0;
+}
+
+long long
+test_set_0_di (void)
+{
+  /* { dg-final { scan-assembler "zero\\tr14(.b0)?, 8" } } */
+  return 0;
+}