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- Log -----------------------------------------------------------------
commit 37ec28ff10428d802d13893c97b0bef7747cc757
Author: Haochen Jiang <[email protected]>
Date: Mon Dec 15 15:18:23 2025 +0800
gcc-12/13/14/15/16: Mention changes for Intel x86_64 and add changes
between minor versions
diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
index 0a091123..6f5d040f 100644
--- a/htdocs/gcc-12/changes.html
+++ b/htdocs/gcc-12/changes.html
@@ -768,6 +768,9 @@ function Multiply (S1, S2 : Sign) return Sign is
AVX512-FP16 intrinsics are available via the <code>-mavx512fp16</code>
compiler switch.
</li>
+ <li>Since GCC 12.5, CLDEMOTE is not enabled through the compiler switch
+ <code>-march=alderlake</code> any longer.
+ </li>
<li>For both C and C++ the <code>_Float16</code> type is supported on
x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
all operations will be emulated in software and <code>float</code>
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 4a7b95d3..b9e7b369 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -668,21 +668,25 @@ You may also want to check out our
</li>
<li>GCC now supports the Intel CPU named Raptor Lake through
<code>-march=raptorlake</code>.
- Raptor Lake is based on Alder Lake.
+ Raptor Lake is based on Alder Lake. Since GCC 13.5, CLDEMOTE is not
+ enabled any longer.
</li>
<li>GCC now supports the Intel CPU named Meteor Lake through
<code>-march=meteorlake</code>.
- Meteor Lake is based on Alder Lake.
+ Meteor Lake is based on Alder Lake. Since GCC 13.5, CLDEMOTE is not
+ enabled any longer.
</li>
<li>GCC now supports the Intel CPU named Sierra Forest through
<code>-march=sierraforest</code>.
- Based on ISA extensions enabled on Alder Lake, the switch further enables
- the AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPccXADD, ENQCMD and UINTR
- ISA extensions.
+ Based on ISA extensions enabled on Alder Lake, the switch in addition
+ enables the AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8 and CMPccXADD ISA
+ extensions. Since GCC 13.2, ENQCMD and UINTR are further enabled.
</li>
<li>GCC now supports the Intel CPU named Grand Ridge through
<code>-march=grandridge</code>.
- Grand Ridge is based on Sierra Forest.
+ Based on Sierra Forest, the switch in addition enables the RAO-INT
+ ISA extensions. Since GCC 13.2, ENQCMD and UINTR are further enabled.
+ Since GCC 13.3, RAO-INT is not enabled any longer.
</li>
<li>GCC now supports the Intel CPU named Emerald Rapids through
<code>-march=emeraldrapids</code>.
@@ -690,14 +694,17 @@ You may also want to check out our
</li>
<li>GCC now supports the Intel CPU named Granite Rapids through
<code>-march=graniterapids</code>.
- Based on Sapphire Rapids, the switch further enables the AMX-FP16 and
+ Based on Sapphire Rapids, the switch in addition enables the AMX-FP16 and
PREFETCHI ISA extensions.
</li>
<li>GCC now supports the Intel CPU named Granite Rapids D through
<code>-march=graniterapids-d</code>.
- Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA
+ Based on Granite Rapids, the switch in addition enables the AMX-COMPLEX ISA
extensions.
</li>
+ <li>Since GCC 13.5, CLDEMOTE is not enabled through the compiler
+ switch <code>-march=alderlake</code> any longer.
+ </li>
<li>GCC now supports AMD CPUs based on the <code>znver4</code> core
via <code>-march=znver4</code>. The switch makes GCC consider
using 512-bit vectors when auto-vectorizing.
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 6be9e55a..5a7190e7 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -968,31 +968,41 @@ __asm (".global __flmap_lock" "\n\t"
</li>
<li>GCC now supports the Intel CPU named Clearwater Forest through
<code>-march=clearwaterforest</code>.
- Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
- PREFETCHI, SHA512, SM3, SM4 and USER_MSR ISA extensions.
+ Based on Sierra Forest, the switch in addition enables the AVX-VNNI-INT16,
+ PREFETCHI, SHA512, SM3, SM4 and USER_MSR ISA extensions. Since GCC 14.4,
+ KL and WIDEKL are not enabled any longer.
</li>
<li>GCC now supports the Intel CPU named Gracemont through
<code>-march=gracemont</code>.
- Gracemont is based on Alder Lake.
+ Gracemont is based on Alder Lake. Since GCC 14.4, CLDEMOTE is not enabled
+ any longer.
</li>
<li>GCC now supports the Intel CPU named Arrow Lake through
<code>-march=arrowlake</code>.
- Based on Alder Lake, the switch further enables the AVX-IFMA,
- AVX-NE-CONVERT, AVX-VNNI-INT8 and CMPccXADD ISA extensions.
+ Based on Alder Lake, the switch in addition enables the AVX-IFMA,
+ AVX-NE-CONVERT, AVX-VNNI-INT8 and CMPccXADD ISA extensions. Since GCC 14.4,
+ CLDEMOTE is not enabled any longer.
</li>
<li>GCC now supports the Intel CPU named Arrow Lake S through
<code>-march=arrowlake-s</code>.
- Based on Arrow Lake, the switch further enables the AVX-VNNI-INT16, SHA512,
- SM3 and SM4 ISA extensions.
+ Based on Arrow Lake, the switch in addition enables the AVX-VNNI-INT16,
+ SHA512, SM3 and SM4 ISA extensions. Since GCC 14.4, CLDEMOTE is not
+ enabled any longer.
</li>
<li>GCC now supports the Intel CPU named Lunar Lake through
<code>-march=lunarlake</code>.
- Lunar Lake is based on Arrow Lake S.
+ Lunar Lake is based on Arrow Lake S. Since GCC 14.4, CLDEMOTE is not
+ enabled any longer.
</li>
<li>GCC now supports the Intel CPU named Panther Lake through
<code>-march=pantherlake</code>.
- Based on Arrow Lake S, the switch further enables the PREFETCHI ISA
- extensions.
+ Based on Arrow Lake S, the switch in addition further enables the PREFETCHI
+ ISA extensions. Since GCC 14.4, CLDEMOTE, KL, PREFETCHI and WIDEKL are
+ not enabled any longer.
+ </li>
+ <li>Since GCC 14.4, CLDEMOTE is not enabled through the compiler
+ switches <code>-march=alderlake</code>, <code>-march=meteorlake</code> and
+ <code>-march=raptorlake</code> any longer.
</li>
<li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are marked
as deprecated. GCC will emit a warning when using the
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index da702185..5c3eee46 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -1242,10 +1242,21 @@ structure used in <code>core 1.49</code>.
</li>
<li>GCC now supports the Intel CPU named Diamond Rapids through
<code>-march=diamondrapids</code>.
- Based on ISA extensions enabled on Granite Rapids D, the switch further
- enables the AMX-AVX512, AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F,
- AVX10.2, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8,
- CMPccXADD, MOVRS, SHA512, SM3, SM4, and USER_MSR ISA extensions.
+ Based on ISA extensions enabled on Granite Rapids D, the switch in addition
+ further enables the AMX-AVX512, AMX-FP8, AMX-MOVRS, AMX-TF32,
AMX-TRANSPOSE,
+ APX_F, AVX10.2, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8,
+ CMPccXADD, MOVRS, SHA512, SM3, SM4, and USER_MSR ISA extensions. Since
+ GCC 15.2, AMX-TRANSPOSE and USER_MSR are not enabled any longer.
+ </li>
+ <li>Since GCC 15.2, CLDEMOTE is not enabled through the compiler
+ switches <code>-march=alderlake</code>, <code>-march=arrowlake</code>,
+ <code>-march=arrowlake-s</code>, <code>-march=gracemont</code>,
+ <code>-march=lunarlake</code>, <code>-march=meteorlake</code>,
+ <code>-march=pantherlake</code> and <code>-march=raptorlake</code> any
+ longer. KL and WIDEKL are not enabled through the compiler switches
+ <code>-march=clearwaterforest</code> and <code>-march=pantherlake</code>
+ any longer. PREFETCHI is not enabled through the compiler switch
+ <code>-march=pantherlake</code> any longer.
</li>
<li>Support for Xeon Phi CPUs (a.k.a. Knight Landing and Knight Mill) were
removed in GCC 15. GCC will no longer accept <code>-march=knl</code>,
diff --git a/htdocs/gcc-16/changes.html b/htdocs/gcc-16/changes.html
index 5891a180..a4a0a3d8 100644
--- a/htdocs/gcc-16/changes.html
+++ b/htdocs/gcc-16/changes.html
@@ -252,6 +252,34 @@ struct Affected : E
<h3 id="x86">IA-32/x86-64</h3>
<ul>
+ <li>GCC now supports the Intel CPU named Wildcat Lake through
+ <code>-march=wildcatlake</code>.
+ Wildcat Lake is based on Panther Lake.
+ </li>
+ <li>GCC now supports the Intel CPU named Nova Lake through
+ <code>-march=novalake</code>.
+ Based on ISA extensions enabled on Panther Lake, the switch in addition
+ enables the APX_F, AVX10.1, AVX10.2 and PREFETCHI ISA extensions.
+ </li>
+ <li>Since GCC 16, AMX-TRANSPOSE and USER_MSR are not enabled through
+ the compiler switch <code>-march=diamondrapids</code> any longer. CLDEMOTE
+ is not enabled through the compiler switches <code>-march=alderlake</code>,
+ <code>-march=arrowlake</code>, <code>-march=arrowlake-s</code>,
+ <code>-march=gracemont</code>, <code>-march=lunarlake</code>,
+ <code>-march=meteorlake</code>, <code>-march=pantherlake</code> and
+ <code>-march=raptorlake</code> any longer. KL and WIDEKL are not enabled
+ through the compiler switches <code>-march=clearwaterforest</code> and
+ <code>-march=pantherlake</code> any longer. PREFETCHI is not enabled
+ through the compiler switch <code>-march=pantherlake</code> any longer.
+ </li>
+ <li><code>-mavx10.1-256</code>, <code>-mavx10.1-512</code>, and
+ <code>-mevex512</code> were removed together with the warning for the
+ behavior change on <code>-mavx10.1</code>. <code>-mavx10.1</code> has
+ enabled AVX10.1 intrinsics with 512-bit vector support since GCC 15.
+ </li>
+ <li>Support for AMX-TRANSPOSE was removed in GCC 16. GCC will no longer
accept
+ <code>-mamx-transpose</code>,
+ </li>
<li>The new <code>--enable-x86-64-mfentry</code> configure option
enables <code>-mfentry</code> which uses <code>__fentry__</code>,
instead of <code>mcount</code> for profiling on x86-64. This
-----------------------------------------------------------------------
Summary of changes:
htdocs/gcc-12/changes.html | 3 +++
htdocs/gcc-13/changes.html | 23 +++++++++++++++--------
htdocs/gcc-14/changes.html | 30 ++++++++++++++++++++----------
htdocs/gcc-15/changes.html | 19 +++++++++++++++----
htdocs/gcc-16/changes.html | 28 ++++++++++++++++++++++++++++
5 files changed, 81 insertions(+), 22 deletions(-)
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