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commit 7314f133f386fd3cc0e95bf266436576f89d335e
Author: Haochen Jiang <haochen.ji...@intel.com>
Date: Wed Aug 28 10:27:36 2024 +0800
gcc-15: Mention recent update for x86_64 backend
Mention AVX10.2 support and Xeon Phi removal in GCC 15.
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 91c020dd..edce138e 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -149,7 +149,23 @@ a work-in-progress.</p>
code like <code>1 << offset</code> is not fast enough.</li>
</ul>
-<!-- <h3 id="x86">IA-32/x86-64</h3> -->
+<h3 id="x86">IA-32/x86-64</h3>
+
+<ul>
+ <li>New ISA extension support for Intel AVX10.2 was added.
+ AVX10.2 intrinsics are available via the <code>-mavx10.2</code> or
+ <code>-mavx10.2-256</code> compiler switch with 256-bit vector size
+ support. 512-bit vector size support for AVX10.2 intrinsics are
+ available via the <code>-mavx10.2-512</code> compiler switch.
+ </li>
+ <li>Support for Xeon Phi CPUs (a.k.a. Knight Landing and Knight Mill) were
+ removed in GCC 15. GCC will no longer accept <code>-march=knl</code>,
+ <code>-march=knm</code>,<code>-mavx5124fmaps</code>,
+ <code>-mavx5124vnniw</code>, <code>-mavx512er</code>,
+ <code>-mavx512pf</code>, <code>-mprefetchwt1</code>,
+ <code>-mtune=knl</code> or <code>-mtune=knm</code> compiler switches.
+ </li>
+</ul>
<!-- <h3 id="mips">MIPS</h3> -->
-----------------------------------------------------------------------
Summary of changes:
htdocs/gcc-15/changes.html | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
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