https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128245
Bug ID: 128245
Summary: Constraint bug in RISC-V backend can result in masked
vlse with v0 destination
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: law at gcc dot gnu.org
Target Milestone: ---
/* { dg-do compile } */
/* { dg-options "-O2 -march=rv64gcv_zvfhmin -mabi=lp64d" } */
#include <riscv_vector.h>
vfloat16m1_t __RTL (startwith ("ira"))
foo (vbool16_t m, _Float16 *p, size_t vl)
{
(function "foo"
(param "m"
(DECL_RTL (reg/v:RVVMF16BI <1> [ m ]))
(DECL_RTL_INCOMING (reg:RVVMF16BI v0 [ m ])))
(param "p"
(DECL_RTL (reg/v:DI <2> [ p ]))
(DECL_RTL_INCOMING (reg:DI a0 [ p ])))
(param "vl"
(DECL_RTL (reg/v:DI <3> [ vl ]))
(DECL_RTL_INCOMING (reg:DI a1 [ vl ])))
(insn-chain
(block 2
(edge-from entry (flags "FALLTHRU"))
(cnote 8 [bb 2] NOTE_INSN_BASIC_BLOCK)
(cinsn 2 (set (reg/v:RVVMF16BI <1> [ m ])
(reg:RVVMF16BI v0 [ m ])))
(cinsn 3 (set (reg/v:DI <2> [ p ])
(reg:DI a0 [ p ])))
(cinsn 4 (set (reg/v:DI <3> [ vl ])
(reg:DI a1 [ vl ])))
(cnote 5 NOTE_INSN_FUNCTION_BEG)
(cinsn 10 (set (reg:RVVM1HF <4>)
(if_then_else:RVVM1HF (unspec:RVVMF16BI [
(reg/v:RVVMF16BI <1> [ m ])
(reg/v:DI <3> [ vl ])
(const_int 2)
(const_int 2)
(const_int 0)
(reg:SI vl)
(reg:SI vtype)
] UNSPEC_VPREDICATE)
(vec_duplicate:RVVM1HF (mem:HF (reg/v:DI <2> [ p ]) [1 *p+0 S2
A16]))
(unspec:RVVM1HF [
(reg:DI zero)
] UNSPEC_VUNDEF))))
(cinsn 11 (set (reg:RVVM1HF v0)
(reg:RVVM1HF <4>)))
(cinsn 12 (use (reg:RVVM1HF v0)))
(edge-to exit (flags "FALLTHRU"))
) ;; block 2
) ;; insn-chain
) ;; function
}
Compiling it gives:
foo:
vsetvli zero,a1,e16,m1,ta,ma
vlse16.v v0,0(a0),zero,v0.t #
*pred_strided_broadcastrvvm1hf_zvfhmin/0
ret
The LLM started with a note that the constraints on the destination operand of
that insn looked wrong. They're currently =vr, vr, vr, vr, but for the masked
alternatives we probably want vd.
