https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123883
--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <[email protected]>: https://gcc.gnu.org/g:c348f5c5e991dd9d4e13d5943485a938cc4342a8 commit r17-2512-gc348f5c5e991dd9d4e13d5943485a938cc4342a8 Author: Dusan Stojkovic <[email protected]> Date: Sat Jul 18 10:38:41 2026 -0600 [PR target/123883] Inefficient bit manipulation code on RISC-V port With changes to the RISC-V backend, it's possible to get the desired code generation for this test with a simple match.pd pattern. Essentially we have (1 << N) & (1 << N) where each shift is in a different type. With some constraints, we can collapse that down to just (1 << N) in the wider type. That in turn allows collapsing the entire sequence down to a single bit set (6 instructions -> 3 instructions on rv64gcb). PR target/123883 gcc/ChangeLog: * match.pd ((1<<N) & (1<<N) with different types): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr123883-a.c: New test. * gcc.target/riscv/pr123883-b.c: New test.
