https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125594
--- Comment #2 from Drea Pinski <pinskia at gcc dot gnu.org> --- (In reply to Drea Pinski from comment #1) > Dup. > > *** This bug has been marked as a duplicate of bug 111126 *** >Other targets like BPF seem better to optimize g1 and g2 to f1 and f2 >respectively since g1/g2 use more registers than f1/f2 and has if condition. Yes that is a known thing we don't do ifcvt on the gimple level always; there are many other issues about that. f1/f2 not using maskeqz is PR 111126 (RV64 with zicond has a similar instruction called czero.eqz. aarch64 code gen is also kinda of odd, cmp/csel should be faster than mul. I think it is the same issue as PR 111126 really because with the current thing expand only tries &=- or *; does not try movcc optab.
