https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115922
Roger Sayle <roger at nextmovesoftware dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2026-05-30
Severity|normal |enhancement
Ever confirmed|0 |1
CC| |roger at nextmovesoftware dot
com
Status|UNCONFIRMED |NEW
--- Comment #2 from Roger Sayle <roger at nextmovesoftware dot com> ---
Interesting. Your "silly patch" is very cool, but I think catching this
optimization in combine has several advantages over implementing it as a
peephole2. The biggest is that for a three->two insn transform, that these
instructions don't need to appear sequentially in the RTL instruction stream
(combine attempts to fuse instructions based on use-def chains, allowing things
to appear in arbitrary order, possibly interspersed with other instructions).
It also avoids reload allocating a register to hold the mask constant that
is ultimately not required.
For the example, -fdump-rtl-combine-all=stdout reports:
Trying 7, 8 -> 9:
7: r198:SI=0xffffffffffff0000
8: r197:SI=r198:SI+0x7fff
REG_DEAD r198:SI
REG_EQUAL 0xffffffffffff7fff
9: r204:SI=r205:SI&r197:SI
REG_DEAD r205:SI
REG_DEAD r197:SI
Failed to match this instruction:
(set (reg:SI 204 [ _2+4 ])
(and:SI (reg:SI 205 [ xD.1930+4 ])
(const_int -32769 [0xffffffffffff7fff])))
Hence, a define_insn_and_split that matches this pattern could be used to
implement this missed optimization. See the patch attached to
PR target/115473 for a similar define_insn_and_split to implement an
optimization during combine.
