https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125411
--- Comment #4 from Joost VandeVondele <Joost.VandeVondele at mat dot ethz.ch> --- (In reply to Richard Biener from comment #3) > I've recently talked with Honza in the context of PGO with atomic counter > updates and we've discussed around eventually optimizing some cases. But > I'm sceptical we can identify safe cases given the optimization barrier they > currently provide also prevents code motion across them. What confuses me is that this is a relaxed atomic store of a type for which stores the HW (IIUC) will do a proper atomic store anyway (probably assuming alignment). Can the compiler not turn these 'relaxed atomic loads/stores' into the corresponding native instructions without side effects? There should not be an optimization barrier?
