https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121426
--- Comment #7 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Stefan Schulze Frielinghaus <[email protected]>: https://gcc.gnu.org/g:2bfd402f8569511901ec8fe7628f57471e6d240a commit r17-438-g2bfd402f8569511901ec8fe7628f57471e6d240a Author: Stefan Schulze Frielinghaus <[email protected]> Date: Mon May 11 08:37:58 2026 +0200 combine: Reject any resulting insns using hard reg constraints [PR121426] This fixes t.c:6:1: error: unable to find a register to spill 6 | } | ^ for target avr. In the PR we are given a patch which makes use of hard register constraints in the machine description for divmodhi4. Prior combine we have for the test from the PR (insn 7 6 8 2 (parallel [ (set (reg:HI 46 [ _1 ]) (div:HI (reg/v:HI 44 [ k ]) (reg:HI 48))) (set (reg:HI 47) (mod:HI (reg/v:HI 44 [ k ]) (reg:HI 48))) (clobber (scratch:HI)) (clobber (scratch:QI)) ]) "t.c":5:5 602 {divmodhi4} (expr_list:REG_DEAD (reg:HI 48) (expr_list:REG_DEAD (reg/v:HI 44 [ k ]) (expr_list:REG_UNUSED (reg:HI 47) (nil))))) (insn 8 7 9 2 (set (reg:HI 22 r22) (symbol_ref/f:HI ("*.LC0") [flags 0x2] <var_decl 0x3fff7950d10 *.LC0>)) "t.c":5:5 128 {*movhi_split} (nil)) (insn 9 8 10 2 (set (reg:HI 24 r24) (reg:HI 46 [ _1 ])) "t.c":5:5 128 {*movhi_split} (expr_list:REG_DEAD (reg:HI 46 [ _1 ]) (nil))) The patched instruction divmodhi4 constraints operand 2 (here pseudo 48) to hard register 22. Combine merges insn 7 into 9 by crossing a hard register assignment of register 22. (note 7 6 8 2 NOTE_INSN_DELETED) (insn 8 7 9 2 (set (reg:HI 22 r22) (symbol_ref/f:HI ("*.LC0") [flags 0x2] <var_decl 0x3fff7950d10 *.LC0>)) "t.c":5:5 128 {*movhi_split} (nil)) (insn 9 8 10 2 (parallel [ (set (reg:HI 24 r24) (div:HI (reg:HI 49 [ k ]) (reg:HI 48))) (set (reg:HI 47) (mod:HI (reg:HI 49 [ k ]) (reg:HI 48))) (clobber (scratch:HI)) (clobber (scratch:QI)) ]) "t.c":5:5 602 {divmodhi4} (expr_list:REG_DEAD (reg:HI 48) (expr_list:REG_DEAD (reg:HI 49 [ k ]) (nil)))) This leaves us with a conflict for pseudo 48 in the updated insn 9 since register 22 is live here. Fixed by pulling the sledge hammer and rejecting any resulting insn which makes use of hard register constraints. Ideally we would skip based on the fact whether a combination crosses a hard register assignment and the corresponding hard register is also referred by a single register constraint of the resulting insn. PR rtl-optimization/121426 gcc/ChangeLog: * combine.cc (recog_for_combine_1): Reject insns which make use of hard register constraints.
