https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121546
--- Comment #4 from Andrew Stubbs <ams at gcc dot gnu.org> --- Valid RTL it might be, but the backend cannot handle such things. We can take a subset of the lane count (V64 -> V32, discarding the other 32 lanes), but amdgcn physically can't do the thing where you change the lane-count but keep the number of bits the same. Each vector is fixed to 64 lanes of 32 or 64 bits each, and we can simulate smaller vector lengths by masking some lanes off. Basically, subregs of vectors are problematic and we don't deliberately use or allow them. (See also pr122583 in which we may be struggling with the same issue.) To do what you want we would use: (subreg:SI (vec_select:DF (reg:V64DF 2724) 0) 0) Except, probably in two steps. I can't comment on the correctness of the fix though.
