This is a recent regression introduced with the following patch, but I
think that it's just uncovered a latent GCSE bug:
2004-11-03 Ulrich Weigand <[EMAIL PROTECTED]>
* tree-ssa-loop-ivopts.c (get_address_cost): Offset zero does not
cause extra costs. Generate canonical RTL.
With the patch applied, we get the following RTL at the start of BB 25 before
GCSE starts to run:
(code_label 236 234 237 25 38 "" [1 uses])
(note 237 236 239 25 [bb 25] NOTE_INSN_BASIC_BLOCK)
(insn 239 237 240 25 (set (reg/f:SI 154 [ D.28277 ])
(const:SI (plus:SI (symbol_ref:SI ("^all_cores") <var_decl 0x4062d740
all_cores>)
(const_int 20 [0x14])))) 143 {*arm_movsi_insn} (nil)
(nil))
(insn 240 239 241 25 (set (reg/v/f:SI 172 [ sel ])
(plus:SI (reg:SI 156 [ ivtmp.895 ])
(reg/f:SI 154 [ D.28277 ]))) 4 {*arm_addsi3} (nil)
(nil))
(insn 241 240 243 25 (set (reg/f:SI 155 [ D.28275 ])
(reg/f:SI 154 [ D.28277 ])) 143 {*arm_movsi_insn} (nil)
(expr_list:REG_EQUAL (const:SI (plus:SI (symbol_ref:SI ("^all_cores")
<var_decl 0x4062d740 all_cores>)
(const_int 20 [0x14])))
(nil)))
GCSE converts this to
(code_label 236 234 237 26 38 "" [1 uses])
(note 237 236 1578 26 [bb 26] NOTE_INSN_BASIC_BLOCK)
(insn 1578 237 240 26 (set (reg/f:SI 154 [ D.28277 ])
(const:SI (plus:SI (symbol_ref:SI ("^all_cores") <var_decl 0x4062d740
all_cores>)
(const_int 20 [0x14])))) 143 {*arm_movsi_insn} (nil)
(expr_list:REG_EQUAL (const:SI (plus:SI (symbol_ref:SI ("^all_cores")
<var_decl 0x4062d740 all_cores>)
(const_int 20 [0x14])))
(nil)))
(insn 240 1578 241 26 (set (reg/v/f:SI 172 [ sel ])
(plus:SI (reg:SI 156 [ ivtmp.895 ])
(reg/f:SI 677 [ D.28277 ]))) 4 {*arm_addsi3} (nil)
(expr_list:REG_EQUAL (plus:SI (reg:SI 156 [ ivtmp.895 ])
(const:SI (plus:SI (symbol_ref:SI ("^all_cores") <var_decl
0x4062d740 all_cores>)
(const_int 20 [0x14]))))
(nil)))
(insn 241 240 1666 26 (set (reg/f:SI 677 [ D.28277 ])
(reg/f:SI 154 [ D.28277 ])) 143 {*arm_movsi_insn} (nil)
(expr_list:REG_EQUAL (const:SI (plus:SI (symbol_ref:SI ("^all_cores")
<var_decl 0x4062d740 all_cores>)
(const_int 20 [0x14])))
(nil)))
But note that now the second real insn uses pseudo 677 which isn't set
until the following instruction. This use before-set causes the
register to be marked live at the start of the BB. However, we
ultimately end up deleting insn 240 entirely and this results in an
abort when we update the register life information.
--
Summary: [4.0.0 Regression] Bootstrap failure on all ARM targets
due to incorrect GCSE
Product: gcc
Version: 4.0.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code, build
Severity: critical
Priority: P1
Component: bootstrap
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: rearnsha at gcc dot gnu dot org
CC: gcc-bugs at gcc dot gnu dot org,law at redhat dot com
GCC target triplet: arm-linux, arm-netbsdelf, arm-elf
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18401
