[Bug target/123501] [16 Regression] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 since g:0b129b8b368635b3170aa276809d644dc99e3256

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123501

--- Comment #1 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Another LMUL corner-case :)  When the mask vector has more than 64 elements
(LMUL4 is enough to trigger a miscompile) we wrongly set its nonzero bit mask
to -127.  The nonzero bits code seems to assume that a popcount:DI always has a
DImode operand but we have e.g. (popcount:DI (V128BImode)).

Testing a patch.