[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Blocks|120763                      |
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #23 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Fixed on the trunk.


Referenced Bugs:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763
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