[Bug target/123010] New: RISC-V: 32-bit multiply by 2 generates slli+srai+slli and doesn't use slliw or addw

[camel-cdr at protonmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123010

            Bug ID: 123010
           Summary: RISC-V: 32-bit multiply by 2 generates slli+srai+slli
                    and doesn't use slliw or addw
           Product: gcc
           Version: 16.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: camel-cdr at protonmail dot com
  Target Milestone: ---

GCC targeting rv64gc turns a signed or unsigned 32-bit multiply by two (a*2 or
a+a) into a three instruction sequence: https://godbolt.org/z/e7ofq8fd9
I've got no idea why it doesn't use slliw or addw, because a multiply by 3 is
sensibly turned into slli+addw.