https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122970
Bug ID: 122970
Summary: RISC-V: Wrong code generated with
-mrvv-vector-bits=zvl for SLP vectorization
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Keywords: wrong-code
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: chenzhongyao.hit at gmail dot com
CC: law at gcc dot gnu.org, rdapp at gcc dot gnu.org
Target Milestone: ---
Target: riscv
Created attachment 62973
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=62973&action=edit
testcase
I discovered this bug while working on RISC-V LMUL cost model tuning.
it's a pre-existing bug in zvl mode.
Tested on trunk commit d3f638f4dfe (20251130).
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$ riscv64-unknown-linux-gnu-gcc --version
riscv64-unknown-linux-gnu-gcc (gd3f638f4dfe) 16.0.0 20251130 (experimental)
Copyright (C) 2025 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ riscv64-unknown-linux-gnu-gcc -O3 -march=rv64gcv -mabi=lp64d
-mrvv-max-lmul=m4 -mrvv-vector-bits=scalable -o test test.c
$ qemu-riscv64 ./test
$ riscv64-unknown-linux-gnu-gcc -O3 -march=rv64gcv -mabi=lp64d
-mrvv-max-lmul=m4 -mrvv-vector-bits=zvl -o test test.c
$ qemu-riscv64 ./test
[1] 1217219 IOT instruction (core dumped) qemu-riscv64 ./test
$
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