[Bug target/122051] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:6011 with -mrvv-vector-bits=zvl -mcpu=xt-c920

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122051

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |law at gcc dot gnu.org
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2025-10-01
             Status|UNCONFIRMED                 |ASSIGNED

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Looks like the implementation of the predicate used by the vector slide is
bogus.

Essentially pmode_reg_or_uimm5_operand is routing through
vector_length_operand.

That was fine until we added thead vector support, but thead vector restricts
constants in some circumstances (particularly in vector lengths).  So the
predicate rejected values 1..31, but the constraint happly accepted those on a
vector slide.

Testing a fix.