https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121867
Bug ID: 121867
Summary: PPC: Misses modulo reduction for constant shift in
AltiVec vec_sl
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: jeevitha at gcc dot gnu.org
Target Milestone: ---
PowerPC has a modulo shift, so it does not matter if higher bits are set in the
shift amount.
For vslb, only the last 3 bits (bits 5–7) are considered.
For vslw, only the last 5 bits (bits 27–31) are considered.
#include <altivec.h>
vector unsigned char shl31(vector unsigned char in)
{
return vec_sl(in, vec_splats((unsigned char)35));
}
Currently on Power8 it generates:
addis 2,12,.TOC.-.LCF0@ha
addi 2,2,.TOC.-.LCF0@l
addis %r9,%r2,.LC0@toc@ha
addi %r9,%r9,.LC0@toc@l
lvx %v0,0,%r9
vslb %v2,%v2,%v0
blr
Should be done by:
On Power8,
vspltisb %v3, 3
vslb %v2, %v2, %v3
blr
On Power9,
xxspltib %vs35, 3
vslb %v2, %v2, %v3
blr
