https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121633
Bug ID: 121633
Summary: missed optimization for carry on ARM
Product: gcc
Version: 15.2.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: Simon.Richter at hogyros dot de
Target Milestone: ---
Compiling
#include <cstdint>
uint64_t maybe_add(uint64_t a, uint64_t b)
{
uint64_t result;
bool const overflow = __builtin_add_overflow(a, b, &result);
if(overflow)
return 0;
return result;
}
with "-O3 -mcpu=cortex-r7" gives
adds r0, r0, r2
adcs r1, r1, r3
mov ip, #0
movcs ip, #1
cmp ip, #0
movne r0, #0
movne r1, r0
bx lr
so the "overflow" variable makes it into a register.
This could be shortened to either
adds r0, r0, r2
adcs r1, r1, r3
movcs r0, #0
movcs r1, #0
bx lr
or
adds r0, r0, r2
adcs r1, r1, r3
bxcc lr
mov r0, #0
mov r1, #0
bx lr
(I'm not sure if it was on ARM that there were some chips that mistakenly clear
C in a MOV instruction)
