[Bug target/121485] RISC-V Zvkned vector-scalar intrinsics use wrong EMUL (m1 for m2/m4/m8 variants of intrinsics)

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121485

Robin Dapp <rdapp at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rdapp at gcc dot gnu.org

--- Comment #1 from Robin Dapp <rdapp at gcc dot gnu.org> ---
The issue is that for the lmul-extending variants the mode attribute is wrong. 
We use the mode of the non-extended operand rather than the extended one.

Something like the following (untested) should help:

 diff --git a/gcc/config/riscv/vector-crypto.md
b/gcc/config/riscv/vector-crypto.md
index ca3ad4412fe..04ae700198b 100644
--- a/gcc/config/riscv/vector-crypto.md
+++ b/gcc/config/riscv/vector-crypto.md
@@ -538,7 +538,7 @@ (define_insn
"@pred_crypto_vv<vv_ins_name><ins_type>x2<mode>_scalar"
   "TARGET_ZVKNED || TARGET_ZVKSED"
   "v<vv_ins_name>.<ins_type>\t%0,%2"
   [(set_attr "type" "v<vv_ins_name>")
-   (set_attr "mode" "<MODE>")])
+   (set_attr "mode" "<VSIX2>mode")])

 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x4<mode>_scalar"
  [(set (match_operand:<VSIX4> 0 "register_operand"      "=&vr")
@@ -556,7 +556,7 @@ (define_insn
"@pred_crypto_vv<vv_ins_name><ins_type>x4<mode>_scalar"
  "TARGET_ZVKNED || TARGET_ZVKSED"
  "v<vv_ins_name>.<ins_type>\t%0,%2"
  [(set_attr "type" "v<vv_ins_name>")
-  (set_attr "mode" "<MODE>")])
+  (set_attr "mode" "<VSIX4>mode")])

 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x8<mode>_scalar"
  [(set (match_operand:<VSIX8> 0 "register_operand"      "=&vr")
@@ -574,7 +574,7 @@ (define_insn
"@pred_crypto_vv<vv_ins_name><ins_type>x8<mode>_scalar"
  "TARGET_ZVKNED || TARGET_ZVKSED"
  "v<vv_ins_name>.<ins_type>\t%0,%2"
  [(set_attr "type" "v<vv_ins_name>")
-  (set_attr "mode" "<MODE>")])
+  (set_attr "mode" "<VSIX8>mode")])

 (define_insn "@pred_crypto_vv<vv_ins_name><ins_type>x16<mode>_scalar"
  [(set (match_operand:<VSIX16> 0 "register_operand"      "=&vr")
@@ -592,7 +592,7 @@ (define_insn
"@pred_crypto_vv<vv_ins_name><ins_type>x16<mode>_scalar"
  "TARGET_ZVKNED || TARGET_ZVKSED"
  "v<vv_ins_name>.<ins_type>\t%0,%2"
  [(set_attr "type" "v<vv_ins_name>")
-  (set_attr "mode" "<MODE>")])
+  (set_attr "mode" "<VSIX16>mode>")])

 ;; vaeskf1.vi vsm4k.vi
 (define_insn "@pred_crypto_vi<vi_ins_name><mode>_scalar"