https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121213
--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:6f63044a7ae63a276a4f6d3108849e093c690bc6 commit r16-3246-g6f63044a7ae63a276a4f6d3108849e093c690bc6 Author: Austin Law <austink...@gmail.com> Date: Sun Aug 17 09:03:51 2025 -0600 [PR target/121213] Avoid unnecessary constant load in amoswap PR 121213 shows an unnecessary "li target,0" in an atomic exchange loop on RISC-V. The source operand for an amoswap instruction should allow (const_int 0) in addition to GPRs. So the operand's predicate is changed to "reg_or_0_operand". The corresponding constraint is also changed to allow a reg or the constant 0. With the source operand no longer tied to the destination operand we do not need the earlyclobber for the destination, so the destination operand's constraint is adjusted accordingly. This patch does not address the unnecessary sign extension reported in the PR. Tested with no regressions on riscv32-elf and riscv64-elf. PR target/121213 gcc/ * config/riscv/sync.md (amo_atomic_exchange<mode>): Allow (const_int 0) as input operand. Do not tie input to output. No longer earlyclobber the output. gcc/testsuite * gcc.target/riscv/amo/pr121213.c: New test.
