[Bug target/121531] [16 Regression] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:10190 with -Os -mcpu=sifive-p670

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121531

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <l...@gcc.gnu.org>:

https://gcc.gnu.org/g:07b74430dffd881177526b4d7e39539c4d676e3a

commit r16-3196-g07b74430dffd881177526b4d7e39539c4d676e3a
Author: Jeff Law <j...@ventanamicro.com>
Date:   Wed Aug 13 17:16:41 2025 -0600

    [RISC-V][PR target/121531] Cover missing insn types in p400 and p600
scheduler models

    So the usual problems, DFAs without full coverage.  I took the output of
Kito's
    checker and use that to construct a dummy reservation for the p400 and p600
    sifive models.

    Tested on riscv32-elf and riscv64-elf with no regressions.

    Pushing to the trunk once pre-commit CI gives the green light.

            PR target/121531
    gcc/
            * config/riscv/sifive-p400.md (sifive_p400_unknown): New
reservation.
            * config/riscv/sifive-p600.md (sifive_p600_unkonwn): Likewise.

    gcc/testsuite/
            * gcc.target/riscv/pr121531.c: New test.