https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121432
--- Comment #11 from Thomas Petazzoni <thomas.petazz...@free-electrons.com> --- So I've been able to narrow down the issue to arch/microblaze/kernel/irq.o. I can't say it's the only file impacted, but as soon as I have this object file from GCC 15.x in my build, it fails The assembly diff between the GCC 14.x file (before) and the GCC 15.x file (after) is as follows: --- before 2025-08-07 11:04:24.561779219 +0200 +++ after 2025-08-07 11:04:14.775803129 +0200 @@ -5,31 +5,30 @@ Disassembly of section .irqentry.text: 00000000 <do_IRQ>: - 0: 3021ffdc addik r1, r1, -36 - 4: fa61001c swi r19, r1, 28 - 8: f9e10000 swi r15, r1, 0 - c: fac10020 swi r22, r1, 32 + 0: 3021ffe0 addik r1, r1, -32 + 4: f9e10000 swi r15, r1, 0 + 8: fa61001c swi r19, r1, 28 + c: f8a10024 swi r5, r1, 36 10: b0000000 imm 0 - 14: eac00000 lwi r22, r0, 0 + 14: ea600000 lwi r19, r0, 0 18: b0000000 imm 0 1c: f8a00000 swi r5, r0, 0 20: b0000000 imm 0 24: b9f40000 brlid r15, 0 - 28: 12650000 addk r19, r5, r0 + 28: 80000000 or r0, r0, r0 2c: b0000000 imm 0 30: e8600000 lwi r3, r0, 0 34: 99fc1800 brald r15, r3 - 38: 10b30000 addk r5, r19, r0 + 38: e8a10024 lwi r5, r1, 36 3c: b0000000 imm 0 40: b9f40000 brlid r15, 0 44: 80000000 or r0, r0, r0 48: e9e10000 lwi r15, r1, 0 4c: b0000000 imm 0 - 50: fac00000 swi r22, r0, 0 + 50: fa600000 swi r19, r0, 0 54: ea61001c lwi r19, r1, 28 - 58: eac10020 lwi r22, r1, 32 - 5c: b60f0008 rtsd r15, 8 - 60: 30210024 addik r1, r1, 36 + 58: b60f0008 rtsd r15, 8 + 5c: 30210020 addik r1, r1, 32 Disassembly of section .init.text: So to me the code is identical to the exception of which registers are used... which makes sense since our problematic GCC commit is about register allocation if I understood correctly (I am not at all a compiler expert). The corresponding C code is pretty short: https://elixir.bootlin.com/linux/v6.16/source/arch/microblaze/kernel/irq.c
